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[Bug target/83488] [8 Regression] ICE on a CET test-case
- From: "igor.v.tsimbalist at intel dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Thu, 21 Dec 2017 16:25:01 +0000
- Subject: [Bug target/83488] [8 Regression] ICE on a CET test-case
- Auto-submitted: auto-generated
- References: <bug-83488-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83488
--- Comment #24 from igor.v.tsimbalist at intel dot com ---
(In reply to Jakub Jelinek from comment #23)
> (In reply to igor.v.tsimbalist from comment #21)
> > Maybe I did more than expected :). Actually 512VNNI has VL bit according to
> > recently published extension. Please see
> >
> > https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> > instruction-set-extensions-programming-reference.pdf
>
> Looking at the same paper, AVX512VPOPCNTDQ is also mixed with AVX512VL,
> though the 128-bit and 256-bit intrinsics and builtins aren't in GCC yet,
> but for
> VNNI there already is avx512vnnivlintrin.h and thus
> __builtin_ia32_vpdpbusd_v8si etc. can use | OPTION_MASK_ISA_AVX512VL after
> your patch immediately.
Agree. Specifying OPTION_MASK_ISA_AVX512VL has to be revised as well as
extension of OPTION_MASK_ISA_AVX512F_UNSET.