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[Bug target/83488] [8 Regression] ICE on a CET test-case
- From: "igor.v.tsimbalist at intel dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Thu, 21 Dec 2017 15:24:39 +0000
- Subject: [Bug target/83488] [8 Regression] ICE on a CET test-case
- Auto-submitted: auto-generated
- References: <bug-83488-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83488
--- Comment #21 from igor.v.tsimbalist at intel dot com ---
Maybe I did more than expected :). Actually 512VNNI has VL bit according to
recently published extension. Please see
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
I can go with my initial patch where I correct just OPTION_MASK_ISA_AVX512F_SET
and leave everything else to an owner of 512vnni implementation. Ok with that?