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[Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv
- From: "ubizjak at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Wed, 20 Dec 2017 10:51:23 +0000
- Subject: [Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv
- Auto-submitted: auto-generated
- References: <bug-83467-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83467
Uroš Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |ASSIGNED
Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com
--- Comment #2 from Uroš Bizjak <ubizjak at gmail dot com> ---
Created attachment 42929
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=42929&action=edit
Prototype patch in testing
Attached patch prevents combine to generate shift insn pattern with hard
registers other than CL in the count operand.