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[Bug tree-optimization/78821] GCC7: Copying whole 32 bits structure field by field not optimised into copying whole 32 bits at once
- From: "jakub at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Mon, 20 Nov 2017 13:37:10 +0000
- Subject: [Bug tree-optimization/78821] GCC7: Copying whole 32 bits structure field by field not optimised into copying whole 32 bits at once
- Auto-submitted: auto-generated
- References: <bug-78821-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78821
--- Comment #26 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Comment on attachment 42661
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=42661
Add bswaphi2 pattern
[(set (match_operand:HI 0 "register_operand")
Is that so that you don't have to bother with forcing operands[1] into a reg if
operands[0] is a MEM and not equal to operands[1]?
The disadvantage of your approach is that the RA will have fewer possibilities
(for -m32 not being able to use %si/%di/%bp, and for all arches not being able
to do 16-bit bswap on memory directly (rolw $8, mem). Guess the latter could
be fixed by another peephole2, the former can't.
On the other side, it has the advantage that flags aren't clobbered from the
beginning, so perhaps sched1 or similar can do a better job.