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[Bug target/82409] Superflous pxor instructions in the generated assembly.
- From: "ubizjak at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Mon, 02 Oct 2017 18:33:37 +0000
- Subject: [Bug target/82409] Superflous pxor instructions in the generated assembly.
- Auto-submitted: auto-generated
- References: <bug-82409-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82409
Uroš Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |RESOLVED
Resolution|--- |INVALID
--- Comment #2 from Uroš Bizjak <ubizjak at gmail dot com> ---
This is by design, to break partial SSE reg dependency on:
/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
destinations to be 128bit to allow register renaming on 128bit SSE units,
but usually results in one extra microop on 64bit SSE units.
Experimental results shows that disabling this option on P4 brings over 20%
SPECfp regression, while enabling it on K8 brings roughly 2.4% regression
that can be partly masked by careful scheduling of moves. */
DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
| m_BDVER | m_ZNVER1 | m_GENERIC)