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[Bug target/81357] Extra mov for zero extend of add
- From: "pinskia at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Thu, 28 Sep 2017 22:37:59 +0000
- Subject: [Bug target/81357] Extra mov for zero extend of add
- Auto-submitted: auto-generated
- References: <bug-81357-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81357
--- Comment #9 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Qing Zhao from comment #8)
> >
> > I don't think there is an easy fix for this example. The compiler believes
> > there are 2 distinct values so it uses 2 registers irrespectively of the order
> > of the mov and uxtw.
>
> then, why when there is NO -fschedule-insns, i.e, when compiled with -O, the
> assembly
> does not have the additional “mov” insn:
> ***/home/qinzhao/Install/latest/bin/gcc -O t.c
> test1:
> add w0, w0, 1
> uxtw x2, w0
> adrp x1, d
> str x2, [x1, #:lo12:d]
> ret
But there is an extra zero extend there instead. Again "uxtw x2, w0" and "mov
w2, w0" for aarch64 are the same exact instruction (same encoding even; just
different aliases for the same instruction); used as uxtw to show it was an
explicit zero extend in the RTL.