[Bug target/81481] [7/8 Regression] Spills %xmm to stack in glibc strspn SSE 4.2 variant

["vmakarov at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81481

--- Comment #4 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
In IRA we have

(insn 9 8 24 2 (set (reg:V2DI 100 [ MEM[(const __m128i_u * {ref-all})_1] ])
        (mem:V2DI (plus:SI (plus:SI (reg:SI 99 [ i ])
                    (reg:SI 87))
                (const:SI (unspec:SI [
                            (symbol_ref:SI ("c") [flags 0x42] <var_decl
0x7f94b4253480 c>)
                        ] UNSPEC_GOTOFF))) [0 MEM[(const __m128i_u *
{ref-all})_1]+0 S16 A8])) "./include/emmintrin.h":702 1233 {movv2di_internal}
     (expr_list:REG_EQUIV (mem:V2DI (plus:SI (plus:SI (reg:SI 99 [ i ])
                    (reg:SI 87))
                (const:SI (unspec:SI [
                            (symbol_ref:SI ("c") [flags 0x42] <var_decl
0x7f94b4253480 c>)
                        ] UNSPEC_GOTOFF))) [0 MEM[(const __m128i_u *
{ref-all})_1]+0 S16 A8])
        (nil)))
(insn 24 9 10 2 (set (reg/v/f:SI 97 [ x ])
        (mem/f/c:SI (reg/f:SI 16 argp) [2 x+0 S4 A32]))
"./include/tmmintrin.h":138 82 {*movsi_internal}
     (expr_list:REG_EQUIV (mem/f/c:SI (reg/f:SI 16 argp) [2 x+0 S4 A32])
        (nil)))
...
(insn 11 10 14 2 (set (reg:V16QI 101)
        (unspec:V16QI [
                (reg:V16QI 102 [ *x_5(D) ])
                (subreg:V16QI (reg:V2DI 100 [ MEM[(const __m128i_u *
{ref-all})_1] ]) 0)
            ] UNSPEC_PSHUFB)) "./include/tmmintrin.h":138 3798
{ssse3_pshufbv16qi3}
     (expr_list:REG_DEAD (reg:V16QI 102 [ *x_5(D) ])
        (expr_list:REG_DEAD (reg:V2DI 100 [ MEM[(const __m128i_u *
{ref-all})_1] ])
            (nil))))

Pseudo 100 gets NO_REGS class in ira-costs.c

  a6 (r100,l0) best NO_REGS, allocno NO_REGS

  a6(r100,l0) costs: SSE_FIRST_REG:0,0 NO_REX_SSE_REGS:0,0 MEM:-9000,-9000

because it is supposed in ira-costs.c that we can remove insn 9 by using equiv
memory for pseudo 100.

LRA does not use this equivalence because the related code in IRA and LRA
is not fully synced.  If the patch will be not ready this week, then it will
be ready only in a week.