[Bug target/79197] [5/6/7 Regression] ICE in extract_insn in gcc/recog.c:2311

["jakub at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79197

--- Comment #9 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Michael Meissner from comment #8)
> I agree the expander should call gpc_reg_operand and not reg_operand.  This
> is due to the fact that on PowerPCs with separate floating point registers,
> SFmode is represented internally as DFmode when it is in the floating
> point/vector registers (i.e. my change on January 4th, 2017).  I evidently
> missed the expander.

The gpc_reg_operand case fixed in a follow-up patch on gcc-patches:
http://gcc.gnu.org/ml/gcc-patches/2017-01/msg02390.html
plus the VSX pattern has been changed to allow DFmode which it didn't allow
before.  Not sure what to do about SFmode though, it might be too large changes
and therefore GCC 8 matter?

> The history is originally we had a define_expand and three separate insns,
> one in rs6000.md that handled the non-VSX case, one in spe.md, and one in
> vsx.md that handled VSX, and it had a common insn for DF, V2DF, and V4SF
> modes.  We later moved the scalar processing to rs6000.md.
> 
> However, since spe.md has its own unsigned fix insns, and it uses wildly
> different constraints, etc. we need to keep a separate define_expand, and
> two define_insns (in rs6000.md and spe.md).
> 
> Note, I have no way of testing SPE, other than by hand inspection of the
> assembly code.

Note SPE only has unsigned_fix:SI mode patterns, not :DI which is what is
problematic here.