[Bug target/78041] Wrong code on ARMv7 with -mthumb -mfpu=neon-fp16 -O0

["wilco at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78041

--- Comment #19 from wilco at gcc dot gnu.org ---
Author: wilco
Date: Tue Jan 24 14:14:12 2017
New Revision: 244872

URL: https://gcc.gnu.org/viewcvs?rev=244872&root=gcc&view=rev
Log:
With -fpu=neon DI mode shifts are expanded after reload.  DI mode registers can 
either fully or partially overlap on both ARM and Thumb-2.  However the shift
expansion code can only deal with the full overlap case, and generates
incorrect
code for partial overlaps.  The fix is to add new variants that support either
full overlap or no overlap.

        Backport from mainline
    gcc/
        PR target/78041
        * config/arm/neon.md (ashldi3_neon): Add "r 0 i" and "&r r i" variants.
        Remove partial overlap check for shift by 1.
        (ashldi3_neon): Likewise.
    testsuite/
        * gcc.target/arm/pr78041.c: New test.

Modified:
    branches/gcc-5-branch/gcc/ChangeLog
    branches/gcc-5-branch/gcc/config/arm/neon.md
    branches/gcc-5-branch/gcc/testsuite/ChangeLog