[Bug target/78823] Poor code on PowerPC when moving SFmode values between GPRs and vector registers

["meissner at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78823

--- Comment #4 from Michael Meissner <meissner at gcc dot gnu.org> ---
Author: meissner
Date: Tue Jan 10 17:44:17 2017
New Revision: 244279

URL: https://gcc.gnu.org/viewcvs?rev=244279&root=gcc&view=rev
Log:
[gcc]
2017-01-10  Michael Meissner  <meissner@linux.vnet.ibm.com>

        Back port from trunk
        2017-01-04  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/71977
        PR target/70568
        PR target/78823
        * config/rs6000/predicates.md (sf_subreg_operand): New predicate.
        (altivec_register_operand): Do not return true if the operand
        contains a SUBREG mixing SImode and SFmode.
        (vsx_register_operand): Likewise.
        (vsx_reg_sfsubreg_ok): New predicate.
        (vfloat_operand): Do not return true if the operand contains a
        SUBREG mixing SImode and SFmode.
        (vint_operand): Likewise.
        (vlogical_operand): Likewise.
        (gpc_reg_operand): Likewise.
        (int_reg_operand): Likewise.
        * config/rs6000/rs6000-protos.h (valid_sf_si_move): Add declaration.
        * config/rs6000/rs6000.c (valid_sf_si_move): New function to
        determine if a MOVSI or MOVSF operation contains SUBREGs that mix
        SImode and SFmode.
        (rs6000_emit_move_si_sf_subreg): New helper function.
        (rs6000_emit_move): Call rs6000_emit_move_si_sf_subreg to possbily
        fixup SUBREGs involving SImode and SFmode.
        * config/rs6000/vsx.md (SFBOOL_*): New constants that are operand
        numbers for the new peephole2 optimization.
        (peephole2 for SFmode unions): New peephole2 to optimize cases in
        the GLIBC math library that do AND/IOR/XOR operations on single
        precision floating point.
        * config/rs6000/rs6000.h (TARGET_NO_SF_SUBREG): New internal
        target macros to say whether we need to avoid SUBREGs mixing
        SImode and SFmode.
        (TARGET_ALLOW_SF_SUBREG): Likewise.
        * config/rs6000/rs6000.md (UNSPEC_SF_FROM_SI): New unspecs.
        (UNSPEC_SI_FROM_SF): Likewise.
        (iorxor): Change spacing.
        (and_ior_xor): New iterator for AND, IOR, and XOR.
        (movsi_from_sf): New insns for SImode/SFmode SUBREG support.
        (movdi_from_sf_zero_ext): Likewise.
        (mov<mode>_hardfloat, FMOVE32 iterator): Use register_operand
        instead of gpc_reg_operand.  Add SImode/SFmode SUBREG support.
        (movsf_from_si): New insn for SImode/SFmode SUBREG support.
        (fma<mode>4): Use gpc_reg_operand instead of register_operand.
        (fms<mode>4): Likewise.
        (fnma<mode>4): Likewise.
        (fnms<mode>4): Likewise.
        (nfma<mode>4): Likewise.
        (nfms<mode>4): Likewise.

        * config/rs6000/rs6000.h (TARGET_DIRECT_MOVE_64BIT): Define macro
        used by the above patch in a limited form.
        * config/rs6000/vsx.md (peephole2 for SFmode unions): Use DFmode
        for doing direct moves instead of DImode, since GCC 6.x does not
        support DImode in Altivec registers.

[gcc/testsuite]
2017-01-10  Michael Meissner  <meissner@linux.vnet.ibm.com>

        Back port from trunk
        2017-01-04  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/71977
        PR target/70568
        PR target/78823
        * gcc.target/powerpc/pr71977-1.c: New tests to check whether on
        64-bit VSX systems with direct move, whether we optimize common
        code sequences in the GLIBC math library for float math functions.
        * gcc.target/powerpc/pr71977-2.c: Likewise.


Added:
    branches/ibm/gcc-6-branch/gcc/testsuite/gcc.target/powerpc/pr71977-1.c
      - copied unchanged from r244232,
trunk/gcc/testsuite/gcc.target/powerpc/pr71977-1.c
    branches/ibm/gcc-6-branch/gcc/testsuite/gcc.target/powerpc/pr71977-2.c
      - copied unchanged from r244232,
trunk/gcc/testsuite/gcc.target/powerpc/pr71977-2.c
Modified:
    branches/ibm/gcc-6-branch/gcc/ChangeLog.ibm
    branches/ibm/gcc-6-branch/gcc/config/rs6000/predicates.md
    branches/ibm/gcc-6-branch/gcc/config/rs6000/rs6000-protos.h
    branches/ibm/gcc-6-branch/gcc/config/rs6000/rs6000.c
    branches/ibm/gcc-6-branch/gcc/config/rs6000/rs6000.h
    branches/ibm/gcc-6-branch/gcc/config/rs6000/rs6000.md
    branches/ibm/gcc-6-branch/gcc/config/rs6000/vsx.md
    branches/ibm/gcc-6-branch/gcc/testsuite/ChangeLog.ibm