[Bug target/78823] New: Poor code on PowerPC when moving SFmode values between GPRs and vector registers

["meissner at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78823

            Bug ID: 78823
           Summary: Poor code on PowerPC when moving SFmode values between
                    GPRs and vector registers
           Product: gcc
           Version: 7.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: meissner at gcc dot gnu.org
  Target Milestone: ---

Created attachment 40344
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40344&action=edit
Sample test file.

The code for moving SFmode values between GPRs and vector registers can be
improved in ISA 2.07 (-mcpu=power8) and ISA 3.0 (-mcpu=power9).

Right now, using a simple test case with a union, -mcpu=power8 generates a
store and load to move a SFmode value from a vector register to a general
purpose register.  However, some code does generate the appropriate moves.

Going the other way, seems to generate the appropriate instructions.

Using the same simple test case on -mcpu=power9, store/load is used in both
cases.