[Bug target/72804] Poor code gen with -mvsx-timode

["bergner at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=72804

--- Comment #2 from Peter Bergner <bergner at gcc dot gnu.org> ---
Actually, enabling the movti_ppc64 isn't correct, since we have a
*vsx_mov<mode>_64bit pattern that covers this.  The problem is that
*vsx_mov<mode>_64bit disparages the GPR alternatives with ?? so we don't use
them at expand time.  Removing those fixes the performance issue and talking
with Mike, those ??'s were just added to try and get -mvsx-timode to work with
reload, which it never did.  Now that we've switched to LRA, those shouldn't be
necessary, so I'm bootstrapping the following patch:

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c  (revision 239144)
+++ gcc/config/rs6000/rs6000.c  (working copy)
@@ -7747,7 +7747,6 @@ reg_offset_addressing_ok_p (machine_mode
     case V2DFmode:
     case V2DImode:
     case V1TImode:
-    case TImode:
     case TFmode:
     case KFmode:
       /* AltiVec/VSX vector modes.  Only reg+reg addressing was valid until
the
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md    (revision 239144)
+++ gcc/config/rs6000/vsx.md    (working copy)
@@ -851,11 +851,11 @@ (define_insn_and_split "*xxspltib_<mode>
    (set_attr "length" "8")])


-;; Prefer using vector registers over GPRs.  Prefer using ISA 3.0's XXSPLTISB
-;; or Altivec VSPLITW 0/-1 over XXLXOR/XXLORC to set a register to all 0's or
-;; all 1's, since the machine does not have to wait for the previous
-;; instruction using the register being set (such as a store waiting on a slow
-;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move.
+;; Prefer using ISA 3.0's XXSPLTISB or Altivec VSPLITW 0/-1 over XXLXOR/XXLORC
+;; to set a register to all 0's or all 1's, since the machine does not have to
+;; wait for the previous instruction using the register being set (such as a
+;; store waiting on a slow instruction). But generate XXLXOR/XXLORC if it will
+;; avoid a register move.

 ;;              VSX store  VSX load   VSX move  VSX->GPR   GPR->VSX    LQ
(GPR)
 ;;              STQ (GPR)  GPR load   GPR store GPR move   XXSPLTIB   
VSPLTISW
@@ -863,8 +863,8 @@ (define_insn_and_split "*xxspltib_<mode>
 (define_insn "*vsx_mov<mode>_64bit"
   [(set (match_operand:VSX_M 0 "nonimmediate_operand"
                "=ZwO,      <VSa>,     <VSa>,     r,         we,        ?wQ,
-                ?&r,       ??r,       ??Y,       ??r,       wo,        v,
-                ?<VSa>,    *r,        v,         ??r,       wZ,        v")
+                ?&r,       r,         Y,         r,         wo,        v,
+                ?<VSa>,    *r,        v,         r,         wZ,        v")

        (match_operand:VSX_M 1 "input_operand" 
                "<VSa>,     ZwO,       <VSa>,     we,        r,         r,