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[Bug target/68416] [MPX] GCC emits a lot of redundant bndmov instructions
- From: "vmakarov at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Tue, 24 Nov 2015 19:21:39 +0000
- Subject: [Bug target/68416] [MPX] GCC emits a lot of redundant bndmov instructions
- Auto-submitted: auto-generated
- References: <bug-68416-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68416
Vladimir Makarov <vmakarov at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |vmakarov at gcc dot gnu.org
--- Comment #3 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
The first I thought it is a LRA inheritance bug but after more thorough
analysis I found that the problem comes from IRA. IRA never assigns BND hard
registers to pseudos because it never assigns BNDREGS class to pseudos. After
some investigation I found that ALL_REGS does not contain BNDREGS. IRA starts
with ALL_REGS and uses narrow reg class if the mode is prohibited for some hard
registers. That is why class BNDREGS is never used for pseudos.
The following patch solves the problem:
Index: config/i386/i386.h
===================================================================
--- config/i386/i386.h (revision 230664)
+++ config/i386/i386.h (working copy)
@@ -1457,7 +1457,7 @@ enum reg_class
{ 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \
{ 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \
{ 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \
-{ 0xffffffff,0xffffffff, 0x1fff } \
+{ 0xffffffff,0xffffffff,0x1ffff } \
}
/* The same information, inverted:
Please, submit the patch to the trunk.