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[Bug target/68102] New: [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64
- From: "zsojka at seznam dot cz" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Mon, 26 Oct 2015 17:17:11 +0000
- Subject: [Bug target/68102] New: [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64
- Auto-submitted: auto-generated
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68102
Bug ID: 68102
Summary: [5/6 Regression] ICE: RTL check: expected code 'reg',
have 'subreg' in rhs_regno, at rtl.h:1782 with
float64x1_t @ aarch64
Product: gcc
Version: 6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: zsojka at seznam dot cz
Target Milestone: ---
Created attachment 36591
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36591&action=edit
reduced testcase
This might be a fallback of PR60825.
The code ICEs with:
typedef __Float64x1_t float64x1_t;
but works with:
typedef double float64x1_t;
which was the case for 4.x
The code has #include "arm_neon.h", but it can be changed to the typedef above.
RTL checking is needed to get this ICE.
Compiler output:
$ gcc -O2 testcase.c
testcase.c: In function 'foo':
testcase.c:20:1: internal compiler error: RTL check: expected code 'reg', have
'subreg' in rhs_regno, at rtl.h:1782
}
^
0xa90e27 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
char const*)
/mnt/svn/gcc-trunk/gcc/rtl.c:811
0x55f883 rhs_regno
/mnt/svn/gcc-trunk/gcc/rtl.h:1782
0x10571a6 rhs_regno
/mnt/svn/gcc-trunk/gcc/config/aarch64/atomics.md:510
0x10571a6 split_insns(rtx_def*, rtx_insn*)
/mnt/svn/gcc-trunk/gcc/config/aarch64/aarch64.md:1031
0x7a17b0 try_split(rtx_def*, rtx_insn*, int)
/mnt/svn/gcc-trunk/gcc/emit-rtl.c:3666
0xa4a030 split_insn
/mnt/svn/gcc-trunk/gcc/recog.c:2874
0xa5249f split_all_insns()
/mnt/svn/gcc-trunk/gcc/recog.c:2964
0xa52588 execute
/mnt/svn/gcc-trunk/gcc/recog.c:3881
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <http://gcc.gnu.org/bugs.html> for instructions.
Tested revisions:
r229293 - ICE
5-branch r229292 - ICE (even at -O1)
4_9-branch r229291 - OK (it is using the other typedef)
- Follow-Ups:
- [Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64
- From: zsojka at seznam dot cz
- [Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64
- From: rguenth at gcc dot gnu.org
- [Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64
- From: ktkachov at gcc dot gnu.org
- [Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64
- From: ktkachov at gcc dot gnu.org
- [Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64
- From: ktkachov at gcc dot gnu.org
- [Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64
- From: ktkachov at gcc dot gnu.org