[Bug rtl-optimization/67443] [5/6 regression] DSE removes required store instruction

["vogt at linux dot vnet.ibm.com" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67443

--- Comment #7 from Dominik Vogt <vogt at linux dot vnet.ibm.com> ---
Almost.  Note the strange bit numbering on s390.  The highest order bit in any
operation always has the number 0, and the lowest order bit has the highest
number.  So the 8-bit-move instruction "mvi" stores a byte into *a (bit 0-7),
then the 32-bit-and instruction "n" reads *a as a 32 bit value.  The bits 0-7
are the highest order bits of the result, so the value read is actually
0x03xxxxxx (bits 0-7 have the value 0x03, the rest is random data).

(Actually, I couldn't read this assembly code right without the help of a
debugger.)

                       # r2 contains the address a at start of function
  larl  %r5,.L3 
  mvi  0(%r2),3        # b-byte store of value 3 to the *(a + 0) 
                       #   -> memory at a: 03 ** ** ** ** ** ** ** 
  l  %r1,.L4-.L3(%r5)  # 32-bit-load 0xff000000 to r1 

  n  %r1,0(%r2)        # 32-bit "and" of *(a + 0) and $1, result 
                       # stored in r1 -> 0x03000000 

  oill  %r1,5          # 64-bit "or" of r1 with the immediate value 
                       # 0x00000000 00000005 
                       # r1 -> 0x03000005
  st  %r1,0(%r2)       # 32-bit store or r1 to a 
                       #   -> memory at a: 03 00 00 05 ** ** ** ** 
  br  %r14 
.L3: 
.L4: 
  .long  -16777216