[Bug target/67366] Poor assembly generation for unaligned memory accesses on ARM v6 & v7 cpus

["ramana at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67366

--- Comment #15 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
Author: ramana
Revision: 228644
Modified property: svn:log

Modified: svn:log at Fri Oct  9 11:08:05 2015
------------------------------------------------------------------------------
--- svn:log (original)
+++ svn:log Fri Oct  9 11:08:05 2015
@@ -1,45 +1,43 @@
-[AArch64] Handle literal pools for functions > 1 MiB in size.
-    
+[PATCH PR target/67366 2/2] [gimple-fold.c] Support movmisalign optabs in
gimple-fold.c

-This patch fixes the issue in PR63304 where we have
-functions that are > 1MiB. The idea is to use adrp / ldr or adrp / add
-instructions to address the literal pools under the use of a command line
-option. I would like to turn this on by default on trunk but keep this
-disabled by default for the release branches in order to get some
-serious testing for this feature while it bakes on trunk.
+This patch by Richard allows for movmisalign optabs to be supported
+in gimple-fold.c. This caused a bit of pain in the testsuite with
strlenopt-8.c
+in conjunction with the ARM support for movmisalign_optabs as the test
+was coded up to do different things depending on whether the target
+supported misaligned access or not. However now with unaligned access
+being allowed for different levels of the architecture in the arm backend,
+the concept of the helper function non_strict_align mapping identically
+to the definition of STRICT_ALIGNMENT disappears.

-As a follow-up I would like to try and see if estimate_num_insns or
-something else can give us a heuristic to turn this on for "large" functions.
-After all the number of incidences of this are quite low in real life,
-so may be we should look to restrict this use as much as possible on the
-grounds that this code generation implies an extra integer register for
-addressing for every floating point and vector constant and I don't think
-that's great in code that already may have high register pressure.
+Adjusted thusly for ARM. The testsuite/lib changes were tested with an
+arm-none-eabi multilib that included architecture variants that did not
+support unaligned access and architecture variants that did.

-Tested on aarch64-none-elf with no regressions. A previous
-version was bootstrapped and regression tested.
+The testing matrix for this patch was:

-Applied to trunk.
+1. x86_64 bootstrap and regression test - no regressions.
+2. armhf bootstrap and regression test - no regressions.
+3. arm-none-eabi cross build and regression test for

-regards
-Ramana
+{-marm/-march=armv7-a/-mfpu=vfpv3-d16/-mfloat-abi=softfp}
+{-mthumb/-march=armv8-a/-mfpu=crypto-neon-fp-armv8/-mfloat-abi=hard}
+{-marm/-mcpu=arm7tdmi/-mfloat-abi=soft}
+{-mthumb/-mcpu=arm7tdmi/-mfloat-abi=soft}

-2015-09-14  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+with no regressions.

-       PR target/63304
-       * config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Handle
-       nopcrelative_literal_loads.
-       (aarch64_classify_address): Likewise.
-       (aarch64_constant_pool_reload_icode): Define.
-       (aarch64_secondary_reload): Handle secondary reloads for
-       literal pools.
-       (aarch64_override_options): Handle nopcrelative_literal_loads.
-       (aarch64_classify_symbol): Handle nopcrelative_literal_loads.
-       * config/aarch64/aarch64.md
(aarch64_reload_movcp<GPF_TF:mode><P:mode>):
-       Define.
-       (aarch64_reload_movcp<VALL:mode><P:mode>): Likewise.
-       * config/aarch64/aarch64.opt (mpc-relative-literal-loads): New option.
-       * config/aarch64/predicates.md (aarch64_constant_pool_symref): New
-       predicate.
-       * doc/invoke.texi (mpc-relative-literal-loads): Document.
+Ok to apply ?

+2015-10-09  Richard Biener  <rguenth@suse.de>
+
+       PR target/67366
+       * gimple-fold.c (optabs-query.h): Include
+       (gimple_fold_builtin_memory_op): Allow unaligned stores
+       when movmisalign_optabs are available.
+
+2015-10-09  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       PR target/67366
+       * lib/target-supports.exp (check_effective_target_non_strict_align):
+       Adjust for arm*-*-*.
+       * gcc.target/arm/pr67366.c: New test.