[Bug target/65955] New: [arm] ICE during movcond_addsi split

["vries at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65955

            Bug ID: 65955
           Summary: [arm] ICE during movcond_addsi split
           Product: gcc
           Version: 6.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: vries at gcc dot gnu.org
  Target Milestone: ---

When bootstrapping r222257 with ada on arm, I run into this error during
stage2:
...
build/./prev-gcc/xgcc -Bbuild/./prev-gcc/ -Binstall/arm-linux-gnueabihf/bin/
-Binstall/arm-linux-gnueabihf/bin/ -Binstall/arm-linux-gnueabihf/lib/ -isystem
install/arm-linux-gnueabihf/include -isystem
install/arm-linux-gnueabihf/sys-include    -c -g -O2 -gtoggle  -gnatpg -gnata
-W -Wall -nostdinc -I- -I. -Iada/generated -Iada -Isrc/gcc/ada
-Isrc/gcc/ada/gcc-interface src/gcc/ada/sem_eval.adb -o ada/sem_eval.o
+===========================GNAT BUG DETECTED==============================+
| 6.0.0 20150421 (experimental) (arm-linux-gnueabihf) GCC error:           |
| RTL check: expected code 'reg', have 'const_int' in rhs_regno, at        |
|     rtl.h:1710                                                           |
| Error detected around
/home/vries/gcc_versions/devel/src/gcc/ada/sem_eval.adb:2707:8|
| Please submit a bug report; see http://gcc.gnu.org/bugs.html.            |
| Use a subject line meaningful to you and us to track the bug.            |
| Include the entire contents of this bug box in the report.               |
| Include the exact command that you entered.                              |
| Also include sources listed below.                                       |
+==========================================================================+
...

The ICE happens in the movcond_addsi split:
...
#14 0x01073338 in gen_split_2620 (curr_insn=0xb541aa00, operands=0x24df368
<recog_data>) at /home/vries/gcc_versions/devel/src/gcc/config/arm/arm.md:9334
9334        if (REGNO (operands[2]) != REGNO (operands[0]))
...

because operands[2] is not a reg, and we're taking it's regno:
...
(gdb) call debug_rtx (operands[2])
(const_int 0 [0])
...

Aforementioned split (and define_insn) as a whole:
...
  9306  (define_insn_and_split "movcond_addsi"
  9307    [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
  9308          (if_then_else:SI
  9309           (match_operator 5 "comparison_operator"
  9310            [(plus:SI (match_operand:SI 3 "s_register_operand" "r,r,r")
  9311                      (match_operand:SI 4 "arm_add_operand"
"rIL,rIL,rIL"))
  9312              (const_int 0)])
  9313           (match_operand:SI 1 "arm_rhs_operand" "rI,rPy,r")
  9314           (match_operand:SI 2 "arm_rhs_operand" "rI,rPy,r")))
  9315     (clobber (reg:CC CC_REGNUM))]
  9316     "TARGET_32BIT"
  9317     "#"
  9318     "&& reload_completed"
  9319    [(set (reg:CC_NOOV CC_REGNUM)
  9320          (compare:CC_NOOV
  9321           (plus:SI (match_dup 3)
  9322                    (match_dup 4))
  9323           (const_int 0)))
  9324     (set (match_dup 0) (match_dup 1))
  9325     (cond_exec (match_dup 6)
  9326                (set (match_dup 0) (match_dup 2)))]
  9327    "
  9328    {
  9329      machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[5]),
  9330                                               operands[3], operands[4]);
  9331      enum rtx_code rc = GET_CODE (operands[5]);
  9332      operands[6] = gen_rtx_REG (mode, CC_REGNUM);
  9333      gcc_assert (!(mode == CCFPmode || mode == CCFPEmode));
  9334      if (REGNO (operands[2]) != REGNO (operands[0]))
  9335        rc = reverse_condition (rc);
  9336      else
  9337        std::swap (operands[1], operands[2]);
  9338
  9339      operands[6] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6],
const0_rtx);
  9340    }
  9341    "
  9342    [(set_attr "conds" "clob")
  9343     (set_attr "enabled_for_depr_it" "no,yes,yes")
  9344     (set_attr "type" "multiple")]
  9345  )
...

The insn we're trying to split is:
...
(insn 409 64 79 4 (parallel [
            (set (reg:SI 3 r3 [orig:112 D.15185 ] [112])
                (if_then_else:SI (ge (plus:SI (reg:SI 6 r6 [orig:141 D.15193 ]
[141])
                            (const_int -1 [0xffffffffffffffff]))
                        (const_int 0 [0]))
                    (reg:SI 6 r6 [orig:141 D.15193 ] [141])
                    (const_int 0 [0])))
            (clobber (reg:CC 100 cc))
        ]) src/gcc/ada/sem_eval.adb:2658 258 {movcond_addsi}
     (nil))
...