This is the mail archive of the
gcc-bugs@gcc.gnu.org
mailing list for the GCC project.
[Bug rtl-optimization/65135] [5 Regression] Performance regression in pic mode after r220674.
- From: "ysrumyan at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Fri, 20 Feb 2015 13:41:51 +0000
- Subject: [Bug rtl-optimization/65135] [5 Regression] Performance regression in pic mode after r220674.
- Auto-submitted: auto-generated
- References: <bug-65135-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65135
--- Comment #4 from Yuri Rumyantsev <ysrumyan at gmail dot com> ---
This patch improves performance of almost all benchmarks in pic-mode for 32-bit
target, but we have the only huge degradation on benchmark from eembc1.1 suite.
I mentioned that the innermost loop has one more fill.
before r220674
.L8:
testl %esi, %esi
jne .L11
movl 16(%esp), %eax
movl (%eax,%edx), %eax
cmpl $-1, %eax
je .L13
.L43:
movl 4(%esp), %edi
leal 0(,%eax,4), %edx
movl %ecx, %ebx
addl %edx, %edi
cmpl $101, %ecx
je .L41
leal 1(%ebx), %ecx
movl 8(%esp), %ebp
cmpl (%edi), %ebp
jne .L8
after r220674
.L6:
movl 4(%esp), %ebx <-- redundant fill
testl %ebx, %ebx
jne .L9
movl 20(%esp), %eax
movl (%eax,%edx), %eax
cmpl $-1, %eax
je .L11
.L42:
movl 8(%esp), %edi
leal 0(,%eax,4), %edx
movl %ecx, %ebx
addl %edx, %edi
cmpl $101, %ecx
je .L40
leal 1(%ebx), %ecx
movl 12(%esp), %esi
cmpl (%edi), %esi
jne .L6
The issue is that before the fix GOT-register is not considered for allocation
it to physical register.