[Bug rtl-optimization/44281] [4.8/4.9/5 Regression] Global Register variable pessimisation

["law at redhat dot com" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=44281

--- Comment #19 from Jeffrey A. Law <law at redhat dot com> ---
AFAICT the issue with push_flag_into_global_reg_var is poor register
allocation, perhaps made worse by the x86 backend's constrains on the ashldi3_1
insn.


  Loop 0 (parent -1, header bb2, depth 0)
    bbs: 2
    all: 0r96 1r94 2r93 3r92
    modified regnos: 92 93 94 96
    border:
    Pressure: GENERAL_REGS=2
    Hard reg set forest:
      0:( 0-2 4-6 8-15 21-52)@0
        1:( 0-2 4-6 21-52)@0
          2:( 0-2 4-6 37-44)@28000
            3:( 0-2 5 6 37-44)@20000
      Allocno a0r96 of ALL_REGS(46) has 38 avail. regs  0-2 4-6 21-52, node: 
0-2 4-6 21-52 (confl regs =  3 7 16-20 53-79)
      Allocno a1r94 of GENERAL_REGS(14) has 14 avail. regs  0-2 4-6 37-44,
node:  0-2 4-6 37-44 (confl regs =  3 7-36 45-79)
      Allocno a2r93 of GENERAL_REGS(14) has 14 avail. regs  0-2 4-6 37-44,
node:  0-2 4-6 37-44 (confl regs =  3 7-36 45-79)
      Allocno a3r92 of GENERAL_REGS(14) has 13 avail. regs  0-2 5 6 37-44,
node:  0-2 5 6 37-44 (confl regs =  3 4 7-36 45-79)
      Pushing a3(r92,l0)(cost 0)
      Pushing a2(r93,l0)(cost 0)
      Pushing a1(r94,l0)(cost 0)
      Pushing a0(r96,l0)(cost 0)
      Popping a0(r96,l0)  -- assign reg 0
      Popping a1(r94,l0)  -- assign reg 1
      Popping a2(r93,l0)  -- assign reg 4
      Popping a3(r92,l0)  -- assign reg 5
Disposition:
    3:r92  l0     5    2:r93  l0     4    1:r94  l0     1    0:r96  l0     0

In particular note a0(r96) going into reg0.  At that point, we've lost.  We'd
really like to see it go into %ebx, which is a global register variable.  The
key insns are:

(insn 11 10 12 2 (parallel [
            (set (reg:DI 96 [ D.1874 ])
                (ashift:DI (reg/v:DI 3 bx [ global_flag_stack ])
                    (const_int 8 [0x8])))
            (clobber (reg:CC 17 flags))
        ]) j.c:61 511 {*ashldi3_1}
     (expr_list:REG_DEAD (reg/v:DI 3 bx [ global_flag_stack ])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (nil))))
(insn 12 11 0 2 (parallel [
            (set (reg/v:DI 3 bx [ global_flag_stack ])
                (ior:DI (reg:DI 94 [ D.1873 ])
                    (reg:DI 96 [ D.1874 ])))
            (clobber (reg:CC 17 flags))
        ]) j.c:61 400 {*iordi_1}
     (expr_list:REG_DEAD (reg:DI 96 [ D.1874 ])
        (expr_list:REG_DEAD (reg:DI 94 [ D.1873 ])
            (expr_list:REG_UNUSED (reg:CC 17 flags)
                (nil)))))