[Bug target/55212] [SH] Switch to LRA

["kkojima at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212

--- Comment #73 from Kazumoto Kojima <kkojima at gcc dot gnu.org> ---
(In reply to Oleg Endo from comment #71)
> I don't know the details and maybe I'm totally off here ... LRA is being
> used for ARM and there are almost the same amount of GP registers available
> on ARM than on SH.  So either on ARM nobody has checked for such
> regressions, or there's something else going wrong or missing on SH?  Or is
> it maybe really that SH R0-ness thing that makes everything work (or not
> work) totally different?

I'm not sure about ARM.  The problematic cases I've looked at are
high R0 pressure cases and IRA decided to allocate equiv value
registers to memory as most profitable ones.
It looks that the remained code size inflation came from R0-ness,
very limited base+display addressing, only one index register and
so on.  I'll attach the test cases for them to this PR after merge
from trunk and commit current patches.