[Bug target/53513] [SH] Add support for fschg and fpchg insns and improve fenv support

["olegendo at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53513

--- Comment #35 from Oleg Endo <olegendo at gcc dot gnu.org> ---
Created attachment 33745
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=33745&action=edit
Use SImode for FPSCR, add __builtin_sh_get_fpscr, __builtin_sh_set_fpscr

So I ended up removing the usage of PSImode for FPSCR and using SImode instead.
 I've tested this patch on r216173, together with the already applied
attachment 33727 patch, with -m4 -ml and -m4 -mb.  There is one new failure:

FAIL: gcc.c-torture/execute/20021120-1.c   -O2 -flto -fuse-linker-plugin
-fno-fat-lto-objects  (internal compiler error)

error: insn does not satisfy its constraints:
(insn 1491 1489 1176 5 (set (reg:SI 12 r12)
        (plus:SI (reg:SI 13 r13)
            (const_int 24 [0x18]))) 20021120-1.c:39 76 {*addsi3_compact}
     (nil))


20021120-1.c:58:1: internal compiler error: in reload_cse_simplify_operands, at
postreload.c:415
0x8565017 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
    ../../gcc-trunk2/gcc/rtl-error.c:110
0x8565055 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
    ../../gcc-trunk2/gcc/rtl-error.c:121
0x850c0cc reload_cse_simplify_operands
    ../../gcc-trunk2/gcc/postreload.c:415
0x850e5ea reload_cse_simplify
    ../../gcc-trunk2/gcc/postreload.c:127
0x850e5ea reload_cse_regs_1
    ../../gcc-trunk2/gcc/postreload.c:224
0x850e6a2 reload_cse_regs
    ../../gcc-trunk2/gcc/postreload.c:72
0x850e6a2 execute
    ../../gcc-trunk2/gcc/postreload.c:2348


At that place, reload it's trying to stuff with the fpu_switch insn:

(insn 293 1480 1173 5 (parallel [
            (set (mem/c:DF (reg:SI 12 r12) [4 %sfp+-344 S8 A32])
                (reg:DF 70 fr6))
            (use (reg:SI 154 fpscr0))
            (clobber (scratch:SI))
        ]) 20021120-1.c:39 289 {movdf_i4}
     (nil))
(insn 1173 293 1483 5 (parallel [
            (set (reg:SI 12 r12)
                (reg/v:SI 151 ))
            (use (reg:SI 155 fpscr1))
            (use (reg:SI 154 fpscr0))
            (set (reg:SI 155 fpscr1)
                (unspec_volatile:SI [
                        (const_int 0 [0])
                    ] UNSPECV_FPSCR_STAT))
            (set (reg:SI 154 fpscr0)
                (unspec_volatile:SI [
                        (const_int 0 [0])
                    ] UNSPECV_FPSCR_MODES))
        ]) 20021120-1.c:39 434 {fpu_switch}
     (nil))
(insn 1483 1173 1484 5 (set (reg:SI 13 r13)
        (const_int 252 [0xfc])) 20021120-1.c:39 258 {movsi_ie}
     (nil))
(insn 1484 1483 1485 5 (set (reg:SI 13 r13)
        (plus:SI (reg:SI 13 r13)
            (reg/f:SI 15 r15))) 20021120-1.c:39 76 {*addsi3_compact}
     (expr_list:REG_EQUIV (plus:SI (reg/f:SI 15 r15)
            (const_int 252 [0xfc]))
        (nil)))
(insn 1485 1484 1174 5 (set (mem/c:SI (plus:SI (reg:SI 13 r13)
                (const_int 24 [0x18])) [4 %sfp+-76 S4 A32])
        (reg:SI 12 r12)) 20021120-1.c:39 258 {movsi_ie}
     (nil))
(note 1174 1485 1490 5 NOTE_INSN_DELETED)
(insn 1490 1174 1175 5 (set (reg:SI 13 r13)
        (const_int 524288 [0x80000])) 20021120-1.c:39 258 {movsi_ie}
     (nil))
(insn 1175 1490 1487 5 (set (reg:SI 12 r12)
        (xor:SI (reg:SI 12 r12)
            (reg:SI 13 r13))) 20021120-1.c:39 138 {*xorsi3_compact}
     (nil))
(insn 1487 1175 1488 5 (set (reg:SI 13 r13)
        (const_int 252 [0xfc])) 20021120-1.c:39 258 {movsi_ie}
     (nil))
(insn 1488 1487 1489 5 (set (reg:SI 13 r13)
        (plus:SI (reg:SI 13 r13)
            (reg/f:SI 15 r15))) 20021120-1.c:39 76 {*addsi3_compact}
     (expr_list:REG_EQUIV (plus:SI (reg/f:SI 15 r15)
            (const_int 252 [0xfc]))
        (nil)))
(insn 1489 1488 1491 5 (set (mem/c:SI (plus:SI (reg:SI 13 r13)
                (const_int 24 [0x18])) [4 %sfp+-76 S4 A32])
        (reg:SI 12 r12)) 20021120-1.c:39 258 {movsi_ie}
     (nil))
(insn 1491 1489 1176 5 (set (reg:SI 12 r12)
        (plus:SI (reg:SI 13 r13)
            (const_int 24 [0x18]))) 20021120-1.c:39 76 {*addsi3_compact}
     (nil))
(insn 1176 1491 1496 5 (parallel [
            (set (reg/v:SI 151 )
                (mem/c:SI (reg:SI 12 r12) [4 %sfp+-76 S4 A32]))
            (use (reg:SI 155 fpscr1))
            (use (reg:SI 154 fpscr0))
            (set (reg:SI 155 fpscr1)
                (unspec_volatile:SI [
                        (const_int 0 [0])
                    ] UNSPECV_FPSCR_STAT))
            (set (reg:SI 154 fpscr0)
                (unspec_volatile:SI [
                        (const_int 0 [0])
                    ] UNSPECV_FPSCR_MODES))
        ]) 20021120-1.c:39 434 {fpu_switch}
     (nil))
(insn 1496 1176 1497 5 (set (reg:SI 12 r12)
        (const_int 16 [0x10])) 20021120-1.c:39 258 {movsi_ie}
     (nil))


Summary:

insn 1173 stores the fpscr to r12

the mode switch (xor op) is done on r12

insn 1489 writes r12 (new fpscr value) on the stack

insn 1491 tries to recalculate the stack address and put it into r12, to
satisfy the memory constraints of fpu_switch (which now accepts post-inc load
and simple register address).

insn 1776 tries to load it from the stack


Reload generates a wrong insn addsi3 insn.  Something similar was happening in
PR 55212, too.