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[Bug target/62025] [4.9/4.10 Regression] Miscompilation of openssl sha512.c
- From: "jakub at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Tue, 12 Aug 2014 09:56:55 +0000
- Subject: [Bug target/62025] [4.9/4.10 Regression] Miscompilation of openssl sha512.c
- Auto-submitted: auto-generated
- References: <bug-62025-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62025
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2014-08-12
Ever confirmed|0 |1
--- Comment #11 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
And the bug in that is that in sha1.s (the miscompiled one) sched2 wrongly
scheduled ahi %r8,128 which clobbers %cc in between a %cc producer and %cc
consumer. If I manually fix that up as follows:
--- sha1.s 2014-08-12 08:39:50.694224146 -0400
+++ sha4.s 2014-08-12 09:38:58.914224146 -0400
@@ -6251,8 +6251,8 @@ sha512_block_data_order:
srl %r4,7
n %r11,184(%r15)
al %r3,252(%r8)
+ alc %r2,248(%r8)
ahi %r8,128
- alc %r2,120(%r8)
xr %r11,%r9
st %r11,1072(%r15)
xr %r1,%r5
then the testcase succeeds.
In *.split2 we have:
(insn 11376 7193 11377 5 (parallel [
(set (reg:CCL1 33 %cc)
(compare:CCL1 (plus:SI (reg:SI 3 %r3 [orig:2900 D.1817+4 ]
[2900])
(mem:SI (plus:SI (reg:SI 8 %r8 [orig:65 ivtmp.30 ]
[65])
(const_int 252 [0xfc])) [2 MEM[base: _25,
offset: 248B]+4 S4 A32]))
(reg:SI 3 %r3 [orig:2900 D.1817+4 ] [2900])))
(set (reg:SI 3 %r3 [orig:2900 D.1817+4 ] [2900])
(plus:SI (reg:SI 3 %r3 [orig:2900 D.1817+4 ] [2900])
(mem:SI (plus:SI (reg:SI 8 %r8 [orig:65 ivtmp.30 ] [65])
(const_int 252 [0xfc])) [2 MEM[base: _25, offset:
248B]+4 S4 A32])))
]) 329 {*addsi3_carry1_cc}
(nil))
(insn 11377 11376 7194 5 (parallel [
(set (reg:SI 2 %r2 [ D.1817 ])
(plus:SI (plus:SI (ltu:SI (reg:CCL1 33 %cc)
(const_int 0 [0]))
(reg:SI 2 %r2 [ D.1817 ]))
(mem:SI (plus:SI (reg:SI 8 %r8 [orig:65 ivtmp.30 ] [65])
(const_int 248 [0xf8])) [2 MEM[base: _25, offset:
248B]+0 S4 A64])))
(clobber (reg:CC 33 %cc))
]) 407 {*addsi3_alc}
(expr_list:REG_DEAD (reg:CCL1 33 %cc)
(expr_list:REG_UNUSED (reg:CC 33 %cc)
(nil))))
...
(insn 2799 7206 7208 5 (parallel [
(set (reg:SI 8 %r8 [orig:65 ivtmp.30 ] [65])
(plus:SI (reg:SI 8 %r8 [orig:65 ivtmp.30 ] [65])
(const_int 128 [0x80])))
(clobber (reg:CC 33 %cc))
]) 327 {*addsi3}
(expr_list:REG_UNUSED (reg:CC 33 %cc)
(nil)))
In *.sched2 dump this is (+ is from normal r207605 compilation, - from
FLUSHB=6261 FLUSHE=6263 (i.e. - is working one, + is miscompiled one):
+(insn:TI 11376 2759 2799 5 (parallel [
(set (reg:CCL1 33 %cc)
(compare:CCL1 (plus:SI (reg:SI 3 %r3 [orig:2900 D.1817+4 ]
[2900])
(mem:SI (plus:SI (reg:SI 8 %r8 [orig:65 ivtmp.30 ]
[65])
(const_int 252 [0xfc])) [2 MEM[base: _25,
offset: 248B]+4 S4 A32]))
(reg:SI 3 %r3 [orig:2900 D.1817+4 ] [2900])))
(set (reg:SI 3 %r3 [orig:2900 D.1817+4 ] [2900])
(plus:SI (reg:SI 3 %r3 [orig:2900 D.1817+4 ] [2900])
(mem:SI (plus:SI (reg:SI 8 %r8 [orig:65 ivtmp.30 ] [65])
(const_int 252 [0xfc])) [2 MEM[base: _25, offset:
248B]+4 S4 A32])))
]) 329 {*addsi3_carry1_cc}
(nil))
-(insn:TI 11377 11376 2773 5 (parallel [
+(insn:TI 2799 11376 11377 5 (parallel [
+ (set (reg:SI 8 %r8 [orig:65 ivtmp.30 ] [65])
+ (plus:SI (reg:SI 8 %r8 [orig:65 ivtmp.30 ] [65])
+ (const_int 128 [0x80])))
+ (clobber (reg:CC 33 %cc))
+ ]) 327 {*addsi3}
+ (expr_list:REG_UNUSED (reg:CC 33 %cc)
+ (nil)))
+(insn:TI 11377 2799 2763 5 (parallel [
(set (reg:SI 2 %r2 [ D.1817 ])
(plus:SI (plus:SI (ltu:SI (reg:CCL1 33 %cc)
(const_int 0 [0]))
(reg:SI 2 %r2 [ D.1817 ]))
(mem:SI (plus:SI (reg:SI 8 %r8 [orig:65 ivtmp.30 ] [65])
- (const_int 248 [0xf8])) [2 MEM[base: _25, offset:
248B]+0 S4 A64])))
+ (const_int 120 [0x78])) [2 MEM[base: _25, offset:
248B]+0 S4 A64])))
(clobber (reg:CC 33 %cc))
]) 407 {*addsi3_alc}
(expr_list:REG_DEAD (reg:CCL1 33 %cc)
(expr_list:REG_UNUSED (reg:CC 33 %cc)
(nil))))