[Bug rtl-optimization/57878] Incorrect code: live register clobbered in split2

["eraman at google dot com" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57878

--- Comment #2 from Easwaran Raman <eraman at google dot com> ---
After IRA, we have:

(insn 116 115 117 6 (set (reg:DI 130 [ D.3288 ])
        (mem:DI (plus:SI (reg/v/f:SI 172 [orig:109 __first ] [109])
                (const_int 4 [0x4])) [10 MEM[base: _1, index: _44, offset: 0]+0
S8 A64])) r.ii:197 88 {*movdi_internal}
     (expr_list:REG_EQUIV (mem:DI (plus:SI (reg/v/f:SI 172 [orig:109 __first ]
[109])
                (const_int 4 [0x4])) [10 MEM[base: _1, index: _44, offset: 0]+0
S8 A64])
        (nil)))
(insn 117 116 118 6 (parallel [
            (set (reg/f:SI 138 [ D.3281 ])
                (minus:SI (reg/v/f:SI 173 [orig:110 __cur ] [110])
                    (reg/v/f:SI 103 [ __cur ])))
            (clobber (reg:CC 17 flags))
        ]) 309 {*subsi_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))
(insn 118 117 119 6 (parallel [
            (set (reg/f:SI 140 [ D.3282 ])
                (plus:SI (reg/v/f:SI 103 [ __cur ])
                    (const_int 4 [0x4])))
            (clobber (reg:CC 17 flags))
        ]) 273 {*addsi_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))
(insn 119 118 120 6 (set (mem:DI (plus:SI (reg/v/f:SI 173 [orig:110 __cur ]
[110])
                (const_int 4 [0x4])) [10 MEM[base: _75, index: _77, offset:
0B]+0 S8 A64])
        (reg:DI 130 [ D.3288 ])) r.ii:197 88 {*movdi_internal}
     (expr_list:REG_DEAD (reg:DI 130 [ D.3288 ])
        (nil)))
(insn 120 119 121 6 (set (reg:DI 131 [ D.3287 ])
        (mem:DI (plus:SI (plus:SI (reg/f:SI 99 [ D.3281 ])
                    (reg/f:SI 126 [ D.3282 ]))
                (const_int 8 [0x8])) [10 MEM[base: _1, index: _44, offset: 8]+0
S8 A64])) r.ii:197 88 {*movdi_internal}
     (expr_list:REG_EQUIV (mem:DI (plus:SI (plus:SI (reg/f:SI 99 [ D.3281 ])
                    (reg/f:SI 126 [ D.3282 ]))
                (const_int 8 [0x8])) [10 MEM[base: _1, index: _44, offset: 8]+0
S8 A64])
        (nil)))
(insn 121 120 122 6 (set (mem:DI (plus:SI (plus:SI (reg/f:SI 138 [ D.3281 ])
                    (reg/f:SI 140 [ D.3282 ]))
                (const_int 8 [0x8])) [10 MEM[base: _75, index: _77, offset:
8B]+0 S8 A64])
        (reg:DI 131 [ D.3287 ])) r.ii:197 88 {*movdi_internal}
     (expr_list:REG_DEAD (reg:DI 131 [ D.3287 ])
        (nil)))


After reload,
 1. insn 116 is deleted
 2. In insn 117, the pseudo 138 is replaced with dx
 3. dx is spilled into stack at offset -0x36 from bp.
 4. For insn 119, first a new pseudo 193 is created which is equivalent to 130
and is loaded from memory. This 193 is in DI mode and is replaced by ax. This
would clobber edx, but that is ok since dx is now stored into stack at offset
-0x36.
 5. This is followed by the the store of 193 (ax) into memory location.
 6. Then dx is loaded from bp-0x36.
 7. insn 120 is deleted
 8. For insn 121, the pseudo 131 is replaced by 196 which is assigned the hard
reg ax. 

In the sequence above, shouldn't the fill of dx from bp-0x36 at step 6 above
happen after step 8?