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[Bug rtl-optimization/56181] [4.8 Regression] ICE in verify_loop_structure, at cfgloop.c:1581 with -ftracer
- From: "mpolacek at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Tue, 05 Feb 2013 12:22:28 +0000
- Subject: [Bug rtl-optimization/56181] [4.8 Regression] ICE in verify_loop_structure, at cfgloop.c:1581 with -ftracer
- Auto-submitted: auto-generated
- References: <bug-56181-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56181
--- Comment #3 from Marek Polacek <mpolacek at gcc dot gnu.org> 2013-02-05 12:22:28 UTC ---
Hopefully it'll be somewhat clearer with a picture:
http://people.redhat.com/mpolacek/src/pr56181.png
the BB 4 is the one that is first marked as residing in loop 2 (because it is
dominated by BB 5 and its loop_father is 1, while the loop we're processing is
loop 2).