[Bug middle-end/55889] [4.8 Regression] ICE: in move_op_ascend, at sel-sched.c:6153 with -fschedule-insns -fselective-scheduling

["dje at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55889

--- Comment #22 from David Edelsohn <dje at gcc dot gnu.org> 2013-01-24 02:35:33 UTC ---
I don't understand your analysis.  Prior to sched1, the pr50907.c.205r.asmcons
RTL dump looks like:

(insn 15 14 16 2 (set (reg:SI 3 3)
        (mem/u/c:SI (unspec:SI [
                    (symbol_ref:SI ("*LCM..0") [flags 0x2])
                    (reg:SI 2 2)
                ] UNSPEC_TOCREL) [0 S4 A8]))
/nasfarm/dje/src/src/gcc/testsuite/
gcc.dg/tree-prof/pr50907.c:5 346 {*movsi_internal1}
     (nil))
(insn 16 15 17 2 (set (reg:SI 4 4)
        (mem/u/c:SI (unspec:SI [
                    (symbol_ref/u:SI ("*LC..0") [flags 0x2])
                    (reg:SI 2 2)
                ] UNSPEC_TOCREL) [0 S4 A8]))
/nasfarm/dje/src/src/gcc/testsuite/
gcc.dg/tree-prof/pr50907.c:5 346 {*movsi_internal1}
     (nil))
(insn 17 16 18 2 (parallel [
            (set (reg:SI 3 3)
                (unspec:SI [
                        (reg:SI 3 3)
                        (reg:SI 4 4)
                    ] UNSPEC_TLSTLS))
            (clobber (reg:SI 0 0))
            (clobber (reg:SI 4 4))
            (clobber (reg:SI 5 5))
            (clobber (reg:SI 11 11))
            (clobber (reg:CC 68 0))
            (clobber (reg:SI 65 lr))
        ]) /nasfarm/dje/src/src/gcc/testsuite/gcc.dg/tree-prof/pr50907.c:5 443
{
tls_get_addr_internalsi}
     (expr_list:REG_DEAD (reg:SI 4 4)
        (expr_list:REG_UNUSED (reg:CC 68 0)
            (expr_list:REG_UNUSED (reg:SI 65 lr)
                (expr_list:REG_UNUSED (reg:SI 11 11)
                    (expr_list:REG_UNUSED (reg:SI 5 5)
                        (expr_list:REG_UNUSED (reg:SI 4 4)
                            (expr_list:REG_UNUSED (reg:SI 0 0)
                                (nil)))))))))
(insn 20 18 21 2 (set (reg/f:SI 144 [ __gcov_indirect_call_counters ])
        (mem/u/f/c:SI (reg:SI 3 3) [0 __gcov_indirect_call_counters+0 S4 A32])) 
346 {*movsi_internal1}
     (expr_list:REG_DEAD (reg:SI 3 3)
        (nil)))
(insn 23 22 24 2 (set (reg:SI 148)
        (mem/u/c:SI (unspec:SI [
                    (symbol_ref/u:SI ("*LC..2") [flags 0x2])
                    (reg:SI 2 2)
                ] UNSPEC_TOCREL) [0 S4 A8]))
/nasfarm/dje/src/src/gcc/testsuite/
gcc.dg/tree-prof/pr50907.c:5 346 {*movsi_internal1}
     (nil))
(insn 24 23 25 2 (set (reg:SI 3 3)
        (mem/u/c:SI (unspec:SI [
                    (symbol_ref:SI ("*LCM..2") [flags 0x2])
                    (reg:SI 2 2)
                ] UNSPEC_TOCREL) [0 S4 A8]))
/nasfarm/dje/src/src/gcc/testsuite/
gcc.dg/tree-prof/pr50907.c:5 346 {*movsi_internal1}
     (nil))
(insn 25 24 26 2 (set (reg:SI 4 4)
        (reg:SI 148))
/nasfarm/dje/src/src/gcc/testsuite/gcc.dg/tree-prof/pr5090
7.c:5 346 {*movsi_internal1}
     (nil))
(insn 26 25 27 2 (parallel [
            (set (reg:SI 3 3)
                (unspec:SI [
                        (reg:SI 3 3)
                        (reg:SI 4 4)
                    ] UNSPEC_TLSTLS))
            (clobber (reg:SI 0 0))
            (clobber (reg:SI 4 4))
            (clobber (reg:SI 5 5))
            (clobber (reg:SI 11 11))
            (clobber (reg:CC 68 0))
            (clobber (reg:SI 65 lr))
        ]) /nasfarm/dje/src/src/gcc/testsuite/gcc.dg/tree-prof/pr50907.c:5 443
{
tls_get_addr_internalsi}
     (expr_list:REG_DEAD (reg:SI 4 4)
        (expr_list:REG_UNUSED (reg:CC 68 0)
            (expr_list:REG_UNUSED (reg:SI 65 lr)
                (expr_list:REG_UNUSED (reg:SI 11 11)
                    (expr_list:REG_UNUSED (reg:SI 5 5)
                        (expr_list:REG_UNUSED (reg:SI 4 4)
                            (expr_list:REG_UNUSED (reg:SI 0 0)
                                (nil)))))))))
(insn 29 27 30 2 (set (reg/f:SI 150 [ __gcov_indirect_call_callee ])
        (mem/f/c:SI (reg:SI 3 3) [0 __gcov_indirect_call_callee+0 S4 A32])) 346 
{*movsi_internal1}
     (expr_list:REG_DEAD (reg:SI 3 3)
        (nil)))
(insn 30 29 31 2 (set (reg:SI 3 3)
        (reg/f:SI 144 [ __gcov_indirect_call_counters ])) 346
{*movsi_internal1}
     (expr_list:REG_DEAD (reg/f:SI 144 [ __gcov_indirect_call_counters ])
        (nil)))
(insn 31 30 32 2 (set (reg:DI 4 4)
        (const_int 0 [0])) 367 {*movdi_internal32}
     (nil))


Insns 15 and 16 feed into the TLS call of insn 17.  Insns 23 an 24 feed into
the TLS call of insn 26.

The combine pass converted the original pseudos of insns 13, 14 and 21 into
hard registers. It also combined insns 22 and 24, but left the result in pseudo
r148. Insn 25 moves pseudo r148 into hard register r4, which is used in insn
26.

I do not understand why r65 (LR) is involved or critical, and I do not
understand how the selective scheduler thinks it can move any of those
instructions past one another with the clear control and data dependencies.