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[Bug middle-end/55623] [ARM] GCC should not prefer long dependency chains, they inhibit performance on superscalar processors
- From: "steven at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Sun, 09 Dec 2012 12:13:03 +0000
- Subject: [Bug middle-end/55623] [ARM] GCC should not prefer long dependency chains, they inhibit performance on superscalar processors
- Auto-submitted: auto-generated
- References: <bug-55623-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55623
Steven Bosscher <steven at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |steven at gcc dot gnu.org
--- Comment #6 from Steven Bosscher <steven at gcc dot gnu.org> 2012-12-09 12:13:03 UTC ---
Can you try using -frename-registers?
Without vs with -frename-registers:
mov r3, r0, lsr #2 mov r3, r0, lsr #2
add r3, r3, r0, lsr #1 | add r1, r3, r0, lsr #1
add r3, r3, r0, lsr #3 | add r2, r1, r0, lsr #3
add r3, r3, r0, lsr #4 | add ip, r2, r0, lsr #4
add r3, r3, r0, lsr #5 | add r3, ip, r0, lsr #5
add r3, r3, r0, lsr #6 | add r1, r3, r0, lsr #6
add r3, r3, r0, lsr #7 | add r2, r1, r0, lsr #7
add r3, r3, r0, lsr #8 | add ip, r2, r0, lsr #8
add r3, r3, r0, lsr #9 | add r3, ip, r0, lsr #9
add r3, r3, r0, lsr #10 | add r1, r3, r0, lsr #10
add r3, r3, r0, lsr #11 | add r2, r1, r0, lsr #11
add r3, r3, r0, lsr #12 | add ip, r2, r0, lsr #12
add r3, r3, r0, lsr #13 | add r3, ip, r0, lsr #13
add r3, r3, r0, lsr #14 | add r1, r3, r0, lsr #14
add r3, r3, r0, lsr #15 | add r2, r1, r0, lsr #15
add r3, r3, r0, lsr #16 | add ip, r2, r0, lsr #16
add r3, r3, r0, lsr #17 | add r3, ip, r0, lsr #17
add r3, r3, r0, lsr #18 | add r1, r3, r0, lsr #18
add r3, r3, r0, lsr #19 | add r2, r1, r0, lsr #19
add r3, r3, r0, lsr #20 | add ip, r2, r0, lsr #20
add r3, r3, r0, lsr #21 | add r3, ip, r0, lsr #21
add r3, r3, r0, lsr #22 | add r1, r3, r0, lsr #22
add r3, r3, r0, lsr #23 | add r2, r1, r0, lsr #23
add r0, r3, r0, lsr #24 | add r0, r2, r0, lsr #24
bx lr bx lr