[Bug target/55454] [PPC] unaligned memory accesses do not work correctly for vector extensions when using altivec

["siarhei.siamashka at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55454

--- Comment #3 from Siarhei Siamashka <siarhei.siamashka at gmail dot com> 2012-11-25 19:32:02 UTC ---
Also fails with GCC trunk (gcc version 4.8.0 20120518 (experimental))

The disassembly listing for "init_buffer" function:

00000000 <init_buffer>:
   0:    7d 80 42 a6     mfvrsave r12
   4:    94 21 ff e0     stwu    r1,-32(r1)
   8:    91 81 00 1c     stw     r12,28(r1)
   c:    65 8c 80 00     oris    r12,r12,32768
  10:    7d 80 43 a6     mtvrsave r12
  14:    3d 40 00 00     lis     r10,0
  18:    7c 00 18 ce     lvx     v0,r0,r3
  1c:    39 20 00 0a     li      r9,10
  20:    39 4a 00 00     addi    r10,r10,0
  24:    7c 0a 49 ce     stvx    v0,r10,r9
                        ^^^^
Here it happily tries to use STVX instruction. And using this instruction just
silently aligns the address down to 16 byte boundary, effectively doing the
write at &buffer[0] instead of &buffer[10].

  28:    81 81 00 1c     lwz     r12,28(r1)
  2c:    7d 80 43 a6     mtvrsave r12
  30:    38 21 00 20     addi    r1,r1,32
  34:    4e 80 00 20     blr


And by the way, the memcpy workaround mentioned above is also broken in GCC
4.8, because it tries to be clever and generates exactly the same code relying
on STVX :)


With GCC 4.7.2, at least memcpy variant used to work correctly:

00000000 <init_buffer>:
   0:    3d 40 00 00     lis     r10,0
   4:    80 a3 00 00     lwz     r5,0(r3)
   8:    80 c3 00 04     lwz     r6,4(r3)
   c:    80 e3 00 08     lwz     r7,8(r3)
  10:    39 2a 00 0a     addi    r9,r10,10
  14:    81 03 00 0c     lwz     r8,12(r3)
  18:    90 aa 00 0a     stw     r5,10(r10)
  1c:    90 c9 00 04     stw     r6,4(r9)
  20:    90 e9 00 08     stw     r7,8(r9)
  24:    91 09 00 0c     stw     r8,12(r9)
  28:    4e 80 00 20     blr