[Bug target/39423] [4.6/4.7/4.8 Regression] [SH] performance regression: lost mov @(disp,Rn)

["olegendo at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39423

--- Comment #34 from Oleg Endo <olegendo at gcc dot gnu.org> 2012-08-29 19:05:35 UTC ---
Christian, regarding your message on the patches list:
http://gcc.gnu.org/ml/gcc-patches/2012-08/msg01861.html

I ended up 'fixing' the issue by folding the patterns with iterators. 
Committed with other foldings as rev. 190781.
There are now 3 patterns: "*movsi_index_disp_load", "*movhi_index_disp_load",
"*mov<mode>_index_disp_store".

On a related matter... I've been thinking about PR 50749 (auto-inc-dec
opportunities) and PR 53911 (displacement addressing base address selection).
As far as I understand it, the proper way of fixing those would be implementing
something like General Offset Assignment (GOA) or Address Register Assignment
(ARA).  Just to see how it could be done, I've replaced the auto-inc-dec pass
with my own very early prototype implementation for optimizing address mode
selection (currently only with SH addr modes in mind, but could be extended to
apply to other targets, too).
I'm not sure whether I will be able to get it into shape for 4.8, but early
results show that it conflicts with the combine patterns introduced in the
fixes for this PR, as it would try to turn the scaled index + displacement
addresses into post-inc addresses or normal displacement addresses.  The
problem here is that SH officially does not support scaled index + displacement
addressing, and address mode selection / auto-inc-dec is done before combine.

Anyway, until the proper way has been figured out the combine patterns should
do as a temporary fix.  BTW, DImode and SFmode/DFmode for SH2A are still
missing ...