[Bug target/54168] New: ARM: Redundant instructions emitted at -O3

["mans at mansr dot com" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54168

             Bug #: 54168
           Summary: ARM: Redundant instructions emitted at -O3
    Classification: Unclassified
           Product: gcc
           Version: 4.8.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: mans@mansr.com


Created attachment 27932
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=27932
Test case

Compiling the attached code for ARM results in redundant instructions even at
-O3 optimisation.  Note this sequence (interleaved with other instructions):

        ldrh    r3, [r0]        @ unaligned
        and     r3, r3, #2
        uxth    r3, r3
        cmp     r3, #0
        beq     .L2

The UXTH is clearly redundant since no more than 16 bits can be set by LDRH. 
Once this is removed, the CMP can be folded with the AND as ANDS.

Interestingly, this badness only happens with -march=armv6 or higher.  If the
target is v5, sane code is generated.

This is a regression in the 4.7 and 4.8 branches.  4.6 and earlier behave
properly.