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[Bug target/53949] [SH] Add support for mac.w / mac.l instructions
- From: "olegendo at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Fri, 13 Jul 2012 10:34:20 +0000
- Subject: [Bug target/53949] [SH] Add support for mac.w / mac.l instructions
- Auto-submitted: auto-generated
- References: <bug-53949-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53949
--- Comment #1 from Oleg Endo <olegendo at gcc dot gnu.org> 2012-07-13 10:34:20 UTC ---
(In reply to comment #0)
> So far, GCC does not utilize the integer multiply-add instructions.
> On SH1 only the mac.w instruction is supported.
> On SH2 and above the mac.w and mac.l instructions are available.
>
> Carry over from PR 39423 comment #20
>
> > On a related thread, for further work, I'm thinking on adding support for the
> > MAC instruction, now that was have the multiply and add. But this requires
> > exposing the MACLH registers to reload. Had anyone had a thought on this ? I'd
> > like to give this a try pretty soon.
I think the biggest problem is that the mac operands have to be in memory.
For example:
long long fun (int a, int long b, long long c)
{
return (long long)a * (long long)b + c;
}
would need to become something like ...
mov.l r4,@-r15
mov r15,r1
mov.l r5,@-r15
lds r6,mach
lds r7,macl
mac.l @r15+,@r1+
sts mach,r1
sts macl,r0
rts
add #4,r15
not using the mac instruction seems a bit simpler in this case:
dmuls.l r4,r5
sts mach,r1
clrt
sts macl,r0
addc r6,r0
rts
addc r7,r1
I think the mac instructions can be very useful when they can be used inside of
loops, but for this the whole post-inc memory stuff has to integrate properly
into
the surrounding code.
Chris, do you have any ideas/plans on how to handle the SR.S bit, for example
to implement
the ssmaddhisi4 pattern with mac.w?