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[Bug rtl-optimization/51821] [4.5/4.6/4.7 Regression] 64bit > 32bit conversion produces incorrect results with optimizations
- From: "ubizjak at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Thu, 12 Jan 2012 17:00:48 +0000
- Subject: [Bug rtl-optimization/51821] [4.5/4.6/4.7 Regression] 64bit > 32bit conversion produces incorrect results with optimizations
- Auto-submitted: auto-generated
- References: <bug-51821-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51821
--- Comment #16 from Uros Bizjak <ubizjak at gmail dot com> 2012-01-12 17:00:48 UTC ---
(In reply to comment #15)
> Yes, this seems to be the correct approach.
Patch that fixes the failure:
Index: recog.c
===================================================================
--- recog.c (revision 183053)
+++ recog.c (working copy)
@@ -3038,6 +3038,7 @@ peep2_find_free_register (int from, int to, const
static int search_ofs;
enum reg_class cl;
HARD_REG_SET live;
+ df_ref *def_rec;
int i;
gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
@@ -3051,12 +3052,14 @@ peep2_find_free_register (int from, int to, const
while (from != to)
{
- HARD_REG_SET this_live;
+ gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
+ /* Don't use registers set or clobbered by the insn. */
+ for (def_rec = DF_INSN_DEFS (peep2_insn_data[from].insn);
+ *def_rec; def_rec++)
+ SET_HARD_REG_BIT (live, DF_REF_REGNO (*def_rec));
+
from = peep2_buf_position (from + 1);
- gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
- REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
- IOR_HARD_REG_SET (live, this_live);
}
cl = (class_str[0] == 'r' ? GENERAL_REGS