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[Bug target/48690] gcc-4.3.5 fails for target m68k

From: "diggskevin38 at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
To: gcc-bugs at gcc dot gnu dot org
Date: Wed, 20 Apr 2011 22:05:39 +0000
Subject: [Bug target/48690] gcc-4.3.5 fails for target m68k
Auto-submitted: auto-generated
References: <bug-48690-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48690

--- Comment #13 from diggskevin38 at gmail dot com 2011-04-20 22:05:34 UTC ---
This time without the cut and paste overlap errors (Sorry):

-(define_insn "ashldi_const32"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
-    (ashift:DI (match_operand:DI 1 "general_operand" "ro")
-             (const_int 32)))]
-  ""
-{
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[1]) == REG)
-    operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-  else
-    operands[3] = adjust_address (operands[1], SImode, 4);
-  if (GET_CODE (operands[0]) == REG)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    return "clr%.l %0\;move%.l %3,%0";
-  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return "move%.l %3,%0\;clr%.l %0";
-  else
-    operands[2] = adjust_address (operands[0], SImode, 4);
-  if (ADDRESS_REG_P (operands[2]))
-    return "move%.l %3,%0\;sub%.l %2,%2";
-  else
-    return "move%.l %3,%0\;clr%.l %2";
-})
+(define_insn "*ashldi3_const1"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+    (ashift:DI (match_operand:DI 1 "register_operand" "0")
+           (const_int 1)))]
+  "!TARGET_COLDFIRE"
+  "add%.l %R0,%R0\;addx%.l %0,%0")

-;; The predicate below must be general_operand, because ashldi3 allows that
-(define_insn "ashldi_const"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
-    (ashift:DI (match_operand:DI 1 "general_operand" "0")
-             (match_operand 2 "const_int_operand" "n")))]
-  "(!TARGET_COLDFIRE
-    && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
-    || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
-    || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+    (ashift:DI (match_operand:DI 1 "register_operand" "")
+           (const_int 2)))]
+  "reload_completed && !TARGET_COLDFIRE"
+  [(set (match_dup 0)
+    (ashift:DI (match_dup 1) (const_int 1)))
+   (set (match_dup 0)
+    (ashift:DI (match_dup 0) (const_int 1)))]
+  "")
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+    (ashift:DI (match_operand:DI 1 "register_operand" "")
+           (const_int 3)))]
+  "reload_completed && !TARGET_COLDFIRE"
+  [(set (match_dup 0)
+    (ashift:DI (match_dup 1) (const_int 2)))
+   (set (match_dup 0)
+    (ashift:DI (match_dup 0) (const_int 1)))]
+  "")
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+    (ashift:DI (match_operand:DI 1 "register_operand" "")
+           (const_int 8)))]
+  "reload_completed && !TARGET_COLDFIRE"
+  [(set (match_dup 2)
+    (rotate:SI (match_dup 2) (const_int 8)))
+   (set (match_dup 3)
+    (rotate:SI (match_dup 3) (const_int 8)))
+   (set (strict_low_part (subreg:QI (match_dup 0) 3))
+    (subreg:QI (match_dup 0) 7))
+   (set (strict_low_part (subreg:QI (match_dup 0) 7))
+    (const_int 0))]
 {
-  operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (INTVAL (operands[2]) == 1)
-    return "add%.l %1,%1\;addx%.l %0,%0";
-  else if (INTVAL (operands[2]) == 8)
-    return "rol%.l #8,%1\;rol%.l #8,%0\;move%.b %1,%0\;clr%.b %1";
-  else if (INTVAL (operands[2]) == 16)
-    return "swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1";
-  else if (INTVAL (operands[2]) == 48)
-    return "mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0";
-  else if (INTVAL (operands[2]) == 2)
-    return "add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0";
-  else if (INTVAL (operands[2]) == 3)
-    return "add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l
%1,%1\;addx%.l %0,%0";
-  else /* 32 < INTVAL (operands[2]) <= 63 */
-    {
-      operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
-      output_asm_insn (INTVAL (operands[2]) <= 8 ? "asl%.l %2,%1" :
-            "moveq %2,%0\;asl%.l %0,%1", operands);
-      return "mov%.l %1,%0\;moveq #0,%1";
-    }
+  operands[2] = gen_highpart (SImode, operands[0]);
+  operands[3] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+    (ashift:DI (match_operand:DI 1 "register_operand" "")
+           (const_int 16)))]
+  "reload_completed && !TARGET_COLDFIRE"
+  [(set (match_dup 2)
+    (rotate:SI (match_dup 2) (const_int 16)))
+   (set (match_dup 3)
+    (rotate:SI (match_dup 3) (const_int 16)))
+   (set (strict_low_part (subreg:HI (match_dup 0) 2))
+    (subreg:HI (match_dup 0) 6))
+   (set (strict_low_part (subreg:HI (match_dup 0) 6))
+    (const_int 0))]
+{
+  operands[2] = gen_highpart (SImode, operands[0]);
+  operands[3] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+  [(set (match_operand:DI 0 "pre_dec_operand" "")
+    (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
+           (const_int 32)))]
+  "reload_completed"
+  [(set (match_dup 0) (const_int 0))
+   (set (match_dup 0) (match_dup 1))]
+{
+  operands[0] = adjust_address(operands[0], SImode, 0);
+  operands[1] = gen_lowpart(SImode, operands[1]);
+})
+
+(define_split
+  [(set (match_operand:DI 0 "post_inc_operand" "")
+    (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
+           (const_int 32)))]
+  "reload_completed"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 0) (const_int 0))]
+{
+  operands[0] = adjust_address(operands[0], SImode, 0);
+  operands[1] = gen_lowpart(SImode, operands[1]);
+})
+
+(define_insn_and_split "*ashldi3_const32"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
+    (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
+           (const_int 32)))]
+  ""
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 4) (match_dup 3))
+   (set (match_dup 2) (const_int 0))]
+  "split_di(operands, 2, operands + 2, operands + 4);")
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+    (ashift:DI (match_operand:DI 1 "register_operand" "")
+           (match_operand 2 "const_int_operand" "")))]
+  "reload_completed && !TARGET_COLDFIRE
+   && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
+  [(set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 2)))
+   (set (match_dup 3) (match_dup 4))
+   (set (match_dup 4) (const_int 0))]
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
+  operands[3] = gen_highpart (SImode, operands[0]);
+  operands[4] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+    (ashift:DI (match_operand:DI 1 "register_operand" "")
+           (const_int 48)))]
+  "reload_completed && !TARGET_COLDFIRE"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 2)
+    (rotate:SI (match_dup 2) (const_int 16)))
+   (set (match_dup 3) (const_int 0))
+   (set (strict_low_part (subreg:HI (match_dup 0) 2))
+    (const_int 0))]
+{
+  operands[2] = gen_highpart (SImode, operands[0]);
+  operands[3] = gen_lowpart (SImode, operands[0]);
+})
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+    (ashift:DI (match_operand:DI 1 "register_operand" "")
+           (match_operand 2 "const_int_operand" "")))]
+  "reload_completed && !TARGET_COLDFIRE
+   && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 63"
+  [(set (match_dup 3) (match_dup 2))
+   (set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 3)))
+   (set (match_dup 3) (match_dup 4))
+   (set (match_dup 4) (const_int 0))]
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
+  operands[3] = gen_highpart (SImode, operands[0]);
+  operands[4] = gen_lowpart (SImode, operands[0]);
 })

+(define_insn "*ashldi3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+    (ashift:DI (match_operand:DI 1 "register_operand" "0")
+           (match_operand 2 "const_int_operand" "n")))]
+  "!TARGET_COLDFIRE
+    && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
+    || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
+    || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
+  "#")
+
 (define_expand "ashldi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-    (ashift:DI (match_operand:DI 1 "general_operand" "")
-             (match_operand 2 "const_int_operand" "")))]
+  [(set (match_operand:DI 0 "register_operand" "")
+    (ashift:DI (match_operand:DI 1 "register_operand" "")
+           (match_operand 2 "const_int_operand" "")))]
   "!TARGET_COLDFIRE"
-  "
 {
   /* ???  This is a named pattern like this is not allowed to FAIL based
      on its operands.  */
   if (GET_CODE (operands[2]) != CONST_INT
       || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
       && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
       && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
     FAIL;
-} ")
+})
References:
- [Bug target/48690] New: gcc-4.3.5 fails for target m68k
  - From: diggskevin38 at gmail dot com
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