[Bug target/48126] New: arm_output_sync_loop: misplaced memory barrier, missing clrex / dummy strex

["m.k.edwards at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48126

           Summary: arm_output_sync_loop: misplaced memory barrier,
                    missing clrex / dummy strex
           Product: gcc
           Version: 4.5.2
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: m.k.edwards@gmail.com


Created attachment 23656
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=23656
Patch alters DMB placement and adds CLREXNE

The ARMv6+ implementation of __sync_*_compare_and_swap branches on a failed
compare.  There are two (theoretical, as I understand it) flaws in this branch
path.  One, it skips past the memory barrier at the end of the critical region,
which could cause memory accesses to get speculated in.  Two, it doesn't
perform a clrex (or, for older armv6, a dummy strex) to clear the local
monitor.  This may not be a practical problem in most userland code, but it's
at least not technically correct according to ARM docs, and it interferes with
auditing locking code using valgrind/qemu/etc.

The attached patch fixes these two issues for ARMv7-a / Thumb2 targets. 
However, the "clrexne" part of it is not correct for older ARMv6 variants which
lack clrex or the ability to add a conditional on it (or for assemblers which
can't handle the Thumb2 "it" opcode when assembling for ARM).