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[Bug rtl-optimization/45472] [4.5/4.6 Regression] ICE: in move_op_ascend, at sel-sched.c:6124 with -fselective-scheduling2
- From: "abel at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Thu, 13 Jan 2011 10:04:35 +0000
- Subject: [Bug rtl-optimization/45472] [4.5/4.6 Regression] ICE: in move_op_ascend, at sel-sched.c:6124 with -fselective-scheduling2
- Auto-submitted: auto-generated
- References: <bug-45472-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45472
--- Comment #14 from Andrey Belevantsev <abel at gcc dot gnu.org> 2011-01-13 10:04:18 UTC ---
Do we want at least the patch properly merging the volatile bits in the
scheduler for 4.6? Or is this better be s plain ICE instead of a silent
miscompile?