[Bug insn-scheduling][4.4 ARM] Scheduling error on -O2 -mfloat-abi=softfp -mfpu=vfp

["M.F. Wu" <mingfeng6865 at gmail dot com>]

Dear sir,

gcc-4.4.0 mis-schedules the instructions. It causes the wrong return
values in r0 and r1.
But, gcc-4.5.0 does the right thing to schedule the instructions. How
do I fix this in
gcc-4.4.0? Thank you.

Cheers
Mingfeng



Source code:

typedef unsigned long long float64;

float64 syst_float64_div( float64 a, float64 b )
{
    float64 z;

    *( (double *) &z ) = *( (double *) &a ) / *( (double *) &b );
    return z;

}

Compile options:
-O2 -mfloat-abi=softfp -mfpu=vfp -S

GCC-4.4.0 outputs:
syst_float64_div:
        @ args = 0, pretend = 0, frame = 8
        @ frame_needed = 0, uses_anonymous_args = 0
        @ link register save eliminated.
        fmdrr   d5, r0, r1
        fmdrr   d6, r2, r3
        sub     sp, sp, #8
        ldr     r0, [sp, #0]
        fdivd   d7, d5, d6
        ldr     r1, [sp, #4]
        fstd    d7, [sp, #0]
        add     sp, sp, #8
        bx      lr
        .size   syst_float64_div, .-syst_float64_div

GCC-4.5.0 outputs:
syst_float64_div:
        @ args = 0, pretend = 0, frame = 24
        @ frame_needed = 0, uses_anonymous_args = 0
        @ link register save eliminated.
        sub     sp, sp, #24
        strd    r0, [sp, #8]
        strd    r2, [sp]
        fldd    d7, [sp, #0]
        fldd    d6, [sp, #8]
        fdivd   d7, d6, d7
        fstd    d7, [sp, #16]
        ldr     r0, [sp, #16]
        ldr     r1, [sp, #20]
        add     sp, sp, #24
        bx      lr
        .size   syst_float64_div, .-syst_float64_div