[Bug c/47006] New: ARM: GCC generates faulty assembly code for pre ARMv6 CPUs on unaligned word access

["peterbjorgensen at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47006

           Summary: ARM: GCC generates faulty assembly code for pre ARMv6
                    CPUs on unaligned word access
           Product: gcc
           Version: 4.5.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: peterbjorgensen@gmail.com


arm-elf-gcc produces wrong assembly code for ARM CPU's not supporting unaligned
word access. Prior to ARMv6 word access to non-aligned memory will truncate the
address. Refer to pdf page 76 of
http://www.scss.tcd.ie/~waldroj/3d1/arm_arm.pdf.

Here is the example code:

// compile with:
// arm-elf-gcc -O1 -Wall -g -mcpu=arm7tdmi bug.c
// see disassembly with:
// arm-elf-objdump a.out -d |less 
#include <stdio.h>
int main () {
    char buf[10];
    *((unsigned int*)(buf + 3)) = 0;
    printf(buf);
    return 0;
}

And the disassembly:
00008218 <main>:
    8218:       e92d4010        push    {r4, lr}
    821c:       e24dd00c        sub     sp, sp, #12
    8220:       e3a04000        mov     r4, #0
    8224:       e58d4003        str     r4, [sp, #3]
    8228:       e1a0000d        mov     r0, sp
    822c:       eb00008e        bl      846c <printf>
    8230:       e1a00004        mov     r0, r4
    8234:       e28dd00c        add     sp, sp, #12
    8238:       e8bd8010        pop     {r4, pc}

The instruction "str r4, [sp, #3]" is equivalent to "str r4, [sp]" on the
ARM7TDMI (ARMv4t architecture), as the sp is word aligned. This is not the
intended behaviour of the C program, and no warning is given.

When doing non-aligned word access by the use of a 'packed' struct, GCC
correctly produces multiple byte access instructions.