[Bug rtl-optimization/45472] [4.5/4.6 Regression] ICE: in move_op_ascend, at sel-sched.c:6124 with -fselective-scheduling2

["amonakov at gcc dot gnu dot org" <gcc-bugzilla at gcc dot gnu dot org>]

------- Comment #4 from amonakov at gcc dot gnu dot org  2010-09-20 14:49 -------
A small testcase to illustrate the problem with volatile fields.

//---8<---
struct vv {volatile long a, b;} vv1, vv2;

int foo()
{
  vv1 = vv2;
}
//---8<---

gcc/cc1 -O2 -frename-registers -fschedule-insns2 vol.c

    movq    vv2+8(%rip), %rax
    movq    vv2(%rip), %rdx
    movq    %rax, vv1+8(%rip)
    movq    %rdx, vv1(%rip)

The compiler reorders accesses to volatile fields.  As Andrey said, /v bits are
missing on MEMs even in the .expand dump.


-- 

amonakov at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |amonakov at gcc dot gnu dot
                   |                            |org


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45472