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[Bug middle-end/40386] wrong code generation for several SPEC CPU2000 benchmarks (lucas, mgrid, face, applu, apsi) with -O1 -fno-ira-share-spill-slots
- From: "vmakarov at redhat dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 8 Sep 2010 17:44:34 -0000
- Subject: [Bug middle-end/40386] wrong code generation for several SPEC CPU2000 benchmarks (lucas, mgrid, face, applu, apsi) with -O1 -fno-ira-share-spill-slots
- References: <bug-40386-13613@http.gcc.gnu.org/bugzilla/>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Comment #9 from vmakarov at redhat dot com 2010-09-08 17:44 -------
The problem is in that pseudos (r121 in our case) spilled by IRA are
not added to live_throughout of reload chain. As the result,
pseudo_forbidden_regs are not set up for such pseudos and they can get
a hard registers (42 in our case) even if they live through insns
(insn 153 in our case) using reload (0th in our case) with this
register when another pseudo is spilled and reload ask IRA to assign
the correspodning hard register to other pseudo.
Here are some parts of IRA dump:
Spilling for insn 153.
Using reg 2 for reload 1
Using reg 42 for reload 0
...
Spilling for insn 238.
Using reg 2 for reload 0
Spill 117(a35), cost=5000
Spilled regs 117
Try assign 121(a6), cost=5000: reassign to 42
The fix is pretty simple. I'll send it soon.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40386