[Bug regression/43892] PowerPC suboptimal "add with carry" optimization

["joakim dot tjernlund at transmode dot se" <gcc-bugzilla at gcc dot gnu dot org>]

------- Comment #11 from joakim dot tjernlund at transmode dot se  2010-05-21 06:23 -------
(In reply to comment #10)
> > On my mpc8321 it is a big difference(don't have numbers handy). Why would
> > such a simply insn be a problem performance wise?
> > I know the kernel still uses the carry insn's for calculating the
> > Internet checksum.
> 
> mpc8321 is a relatively simplistic pipeline.  Processors like POWER4, 5, 6, 7
> may not have the same characteristics.  Even with carry bit register renaming,
> it is an extra input/output to a dedicated resource, an extra register port.
> 
> XLC currently avoids carry completely for POWER5 and POWER6:

Avoids? I was under the impression the gcc doesn't try to be smart
yet so no ppc CPU gets to use the "add with carry" insn yet.

> 
> .add32carry:
>         add     r5,r3,r4
>         cmpl    0,0,r5,r4
>         addi    r3,r5,1
>         bclr    BO_IF,CR0_LT
>         ori     r3,r5,0x0000
>         blr
> 
> One cannot assume that fewer UISA instructions equates with fewer
> microarchitecture operations and faster performance.

If this is the case for something as simple as add with carry, one really
needs a simple way to tell gcc what ppc class CPU one wants to use.
Otherwise only the fastest CPUs gets optimal code and the rest, that
really needs fast code, gets punished.


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43892