This is the mail archive of the gcc-bugs@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[Bug target/35363] Missing bit field coalescing optimization



------- Comment #6 from rguenth at gcc dot gnu dot org  2008-02-25 18:54 -------
The IL after MEM_REF lowering looks like

bar ()
{
  int D.1193;
  unsigned int D.1192;
  unsigned int D.1191;
  unsigned int D.1190;
  int D.1189;

  D.1189 = MEM <int {0}, &a>;
  D.1190 = (unsigned int) D.1189;
  D.1191 = D.1190 & 192;
  D.1192 = D.1191 | 1048602;
  D.1193 = (int) D.1192;
  MEM <int {0}, &a> = D.1193;
  return;
}

foo ()
{
  int MEML.2;
  int MEML.1;
  int MEML.0;

  MEML.0 = MEM <int {0}, &a>;
  MEML.0 = BIT_FIELD_EXPR <MEML.0, 2, 3, 0>;
  MEM <int {0}, &a> = MEML.0;
  MEML.1 = MEM <int {0}, &a>;
  MEML.1 = BIT_FIELD_EXPR <MEML.1, 3, 3, 3>;
  MEM <int {0}, &a> = MEML.1;
  MEML.2 = MEM <int {0}, &a>;
  MEML.2 = BIT_FIELD_EXPR <MEML.2, 8, 17, 8>;
  MEM <int {0}, &a> = MEML.2;
  return;
}


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]