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[Bug target/34932] [avr] ICE in reload
- From: "hutchinsonandy at aim dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 23 Jan 2008 02:50:14 -0000
- Subject: [Bug target/34932] [avr] ICE in reload
- References: <bug-34932-6095@http.gcc.gnu.org/bugzilla/>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Comment #3 from hutchinsonandy at aim dot com 2008-01-23 02:50 -------
The pattern requires operand 1 to be same register as operand 0
Operands 1 & 2 share 2 subregs of same Himode register R22
But should have been solvable without any problem, since HI24 is just right!
QI:21 -> QI:24
HI24 = Zex:QI24 + ZexQI22 voila!
QI22 could have been in top half of HI24. So this also works
HI:22 - > HI:22
HI:24 = Zex:QI24 + ZexQI24
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34932