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[Bug rtl-optimization/33224] failing rtl iv analysis (maybe due to df)
- From: "zadeck at naturalbridge dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 30 Aug 2007 16:52:07 -0000
- Subject: [Bug rtl-optimization/33224] failing rtl iv analysis (maybe due to df)
- References: <bug-33224-6954@http.gcc.gnu.org/bugzilla/>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Comment #6 from zadeck at naturalbridge dot com 2007-08-30 16:52 -------
Subject: Re: failing rtl iv analysis (maybe due
to df)
dorit at gcc dot gnu dot org wrote:
> ------- Comment #5 from dorit at gcc dot gnu dot org 2007-08-30 16:29 -------
>
>> dorit,
>> i am having trouble exactly reproducing this example because you did not
>> give the svn revision and so all of the numbers are a little bit
>> different.
>>
>
> it's revision 127623
>
>
>> However, I am going to submit a patch which improves the dump
>> information a lot for these passes and we should talk about it after we
>> can get on the same page.
>>
>
> I applied your patch, and I'll send you the dump shorlty.
>
>
>> However, from looking at your posting, there are some issues that you
>> may want to look at before we talk:
>> The reaching defs problem makes a scan for all of the defs in the blocks
>> in the region. Once all of the defs are found, they are sorted where
>> the primary key is the regno.
>> The id's (DF_REF_ID) are then assigned based on this sorting. The
>> reaching defs problem actually depends on all of the defs for a regno to
>> be contigious.
>> The DF_REF_IDs are not stable between calls to df_set_blocks and any def
>> outside of the region has an undefined DF_REF_ID.
>> In your posting you have:
>>
>>> Below is the output of df_ref_debug for adef in each iteration of the loop in
>>> latch_dominating_def:
>>> d40 reg 187 bb 3 insn 255 flag 0x0 type 0x0 loc 0xf7da4608(0xf7d9a4e0) chain { }
>>> d93 reg 187 bb 2 insn 40 flag 0x0 type 0x0 loc 0xf7d89cc8(0xf7d9a4e0) chain { }
>>>
>> The number after the first "d" is the DF_REF_ID. Note that they are not
>> contiguous.
>> Given the sorting that occurred, they must be contiguous. I assume from this
>> that
>> someone is holding on to old id's. This is not correct.
>> If you are going to play the game with df_set_blocks, you are allowed to hold
>> onto a
>> def, but not the DF_REF_ID, you cannot look at the DF_REF_ID for a def
>> that is not in the blocks set by df_set_blocks.
>>
>
> are you saying it's safer not to call df_set_blocks in iv_analysis_loop_init?
> (iv-analysis still fails when I do that, but maybe that in turn requires other
> changes?)
>
>
>
When df_analyze is called after a call to df_set_blocks, is invalidates
all of the DF_REF_IDs. Thus you have to keep the df_ref in your hand
If you have some datastructure where you are keeping the DF_REF_IDs for
the induction variables (or any variable), that data structure is
invalid after the calls to df_set_blocks/df_analyze.
>From what I see of your dump. reg 187 has only a single slot in the rd
bit vectors, it is slot 41.
Thus, there is only a single def reaching because there is only a single
def being considered.
There is a line in the dump, right after the line that says "dense
invalidated" that contains a map from reg to slot. The first number in
the [] is first slot position of that reg and the second number is the
number of slots occupied by that reg.
The only thing that you are allowed to do with the DF_REF_ID is to get
it from a df_def
AFTER YOU ARE SURE THAT THE DEF IS IN THE REGION and use the DF_REF_ID
as an index into the rd_bitmaps. If you store the DF_REF_ID and expect
to use it after a call to df_set_blocks/df_analyze you will get the
wrong answer, as you are doing now.
Kenny
;; Function fir (fir)
fir
Dataflow summary:
;; invalidated by call 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9
[9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5]
38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [mq] 65 [lr] 66
[ctr] 68 [0] 69 [1] 73 [5] 74 [6] 75 [7] 76 [xer] 77 [0] 78 [1] 79 [2] 80 [3]
81 [4] 82 [5] 83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 91
[14] 92 [15] 93 [16] 94 [17] 95 [18] 96 [19] 110 [vscr]
;; hardware regs used 1 [1] 67 [ap] 113 [sfp]
;; regular block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; eh block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10
[10] 11 [11] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41
[9] 42 [10] 43 [11] 44 [12] 45 [13] 65 [lr] 67 [ap] 79 [2] 80 [3] 81 [4] 82 [5]
83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 113 [sfp]
;; exit block uses 1 [1] 31 [31] 109 [vrsave] 110 [vscr] 113 [sfp]
;; regs ever live 2[2]
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d0(1){ }d1(3){ }d2(4){ }d3(5){ }d4(6){ }d5(7){
}d6(8){ }d7(9){ }d8(10){ }d9(11){ }d10(31){ }d11(33){ }d12(34){ }d13(35){
}d14(36){ }d15(37){ }d16(38){ }d17(39){ }d18(40){ }d19(41){ }d20(42){ }d21(43){
}d22(44){ }d23(45){ }d24(65){ }d25(67){ }d26(79){ }d27(80){ }d28(81){ }d29(82){
}d30(83){ }d31(84){ }d32(85){ }d33(86){ }d34(87){ }d35(88){ }d36(89){ }d37(90){
}d38(113){ }}
;; bb 0 artificial_uses: { }
;; lr in 2 [2] 109 [vrsave] 110 [vscr]
;; lr use
;; lr def 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11
[11] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42
[10] 43 [11] 44 [12] 45 [13] 65 [lr] 67 [ap] 79 [2] 80 [3] 81 [4] 82 [5] 83 [6]
84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 113 [sfp]
;; live in
;; live gen 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11
[11] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42
[10] 43 [11] 44 [12] 45 [13] 65 [lr] 67 [ap] 79 [2] 80 [3] 81 [4] 82 [5] 83 [6]
84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 113 [sfp]
;; live kill
;; lr out 1 [1] 2 [2] 31 [31] 67 [ap] 109 [vrsave] 110 [vscr] 113 [sfp]
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp]
( 0 )->[2]->( 3 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(1){ }u1(31){ }u2(67){ }u3(113){ }}
;; lr in 1 [1] 2 [2] 31 [31] 67 [ap] 109 [vrsave] 110 [vscr] 113 [sfp]
;; lr use 1 [1] 2 [2] 31 [31] 67 [ap] 113 [sfp]
;; lr def 180 181 182 183 184 185 186 187 189 193 316 317 318 319
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen 180 181 182 183 184 185 186 187 189 193 316 317 318 319
;; live kill
;; lr out 1 [1] 31 [31] 67 [ap] 109 [vrsave] 110 [vscr] 113 [sfp] 180
181 182 183 184 185 186 187 189 316 317 318 319
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319
( 2 5 )->[3]->( 5 4 )
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u14(1){ }u15(31){ }u16(67){ }u17(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319
;; lr def 144 146 147 148 149 150 151 152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 178 179 180
181 182 183 184 185 186 187 188 190 192 195 196 197 198 199 200 201 202 203 204
205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
225 226 227 228 229 231 232 233 234 235 236 237 238 239 240 242 243 244 245 246
247 248 249 250 251 253 254 255 256 257 258 259 260 261 262 264 265 266 267 268
269 270 271 272 273 275 276 277 278 279 280 281 282 283 284 285 287 288 289 290
291 292 293 294 295 296 297 299 300 301 302 303 304 305 306 307 308 309 311 313
315 319
;; live in 180 181 182 183 184 185 186 187 319
;; live gen 144 146 147 148 149 150 151 152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 178 179 180
181 182 183 184 185 186 187 188 190 192 195 196 197 198 199 200 201 202 203 204
205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
225 226 227 228 229 231 232 233 234 235 236 237 238 239 240 242 243 244 245 246
247 248 249 250 251 253 254 255 256 257 258 259 260 261 262 264 265 266 267 268
269 270 271 272 273 275 276 277 278 279 280 281 282 283 284 285 287 288 289 290
291 292 293 294 295 296 297 299 300 301 302 303 304 305 306 307 308 309 311 313
315 319
;; live kill
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319
;; live out 180 181 182 183 184 185 186 187 319
( 3 )->[5]->( 3 )
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u-1(1){ }u-1(31){ }u-1(67){ }u-1(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def
;; live in 180 181 182 183 184 185 186 187 319
;; live gen
;; live kill
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319
;; live out 180 181 182 183 184 185 186 187 319
( 3 )->[4]->( 1 )
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u347(1){ }u348(31){ }u349(67){ }u350(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 109 [vrsave] 110 [vscr] 113 [sfp]
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen
;; live kill
;; lr out 1 [1] 31 [31] 67 [ap] 109 [vrsave] 110 [vscr] 113 [sfp]
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp]
( 4 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u351(1){ }u352(31){ }u353(109){ }u354(110){
}u355(113){ }}
;; lr in 1 [1] 31 [31] 109 [vrsave] 110 [vscr] 113 [sfp]
;; lr use 1 [1] 31 [31] 109 [vrsave] 110 [vscr] 113 [sfp]
;; lr def
;; live in 1 [1] 31 [31] 113 [sfp]
;; live gen
;; live kill
;; lr out
;; live out
;; *** Considering loop 1 for complete peeling ***
;; Considering peeling once rolling loop
starting the processing of deferred insns
ending the processing of deferred insns
setting blocks to analyze 3, 5
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
starting region dump
fir
Dataflow summary:
def_info->table_size = 168, use_info->table_size = 356
;; invalidated by call 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9
[9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5]
38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [mq] 65 [lr] 66
[ctr] 68 [0] 69 [1] 73 [5] 74 [6] 75 [7] 76 [xer] 77 [0] 78 [1] 79 [2] 80 [3]
81 [4] 82 [5] 83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 91
[14] 92 [15] 93 [16] 94 [17] 95 [18] 96 [19] 110 [vscr]
;; hardware regs used 1 [1] 67 [ap] 113 [sfp]
;; regular block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; eh block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10
[10] 11 [11] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41
[9] 42 [10] 43 [11] 44 [12] 45 [13] 65 [lr] 67 [ap] 79 [2] 80 [3] 81 [4] 82 [5]
83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 113 [sfp]
;; exit block uses 1 [1] 31 [31] 109 [vrsave] 110 [vscr] 113 [sfp]
;; regs ever live 2[2]
;; Reaching defs:
sparse invalidated
dense invalidated
144[0,1] 146[1,1] 147[2,1] 148[3,1] 149[4,1] 150[5,1] 151[6,1] 152[7,1]
153[8,1] 154[9,1] 155[10,1] 156[11,1] 157[12,1] 158[13,1] 159[14,1] 160[15,1]
161[16,1] 162[17,1] 163[18,1] 164[19,1] 165[20,1] 166[21,1] 167[22,1] 168[23,1]
169[24,1] 170[25,1] 171[26,1] 172[27,1] 173[28,1] 174[29,1] 175[30,1] 176[31,1]
178[32,1] 179[33,1] 180[34,1] 181[35,1] 182[36,1] 183[37,1] 184[38,1] 185[39,1]
186[40,1] 187[41,1] 188[42,1] 190[43,1] 192[44,1] 195[45,1] 196[46,1] 197[47,1]
198[48,1] 199[49,1] 200[50,1] 201[51,1] 202[52,1] 203[53,2] 204[55,1] 205[56,1]
206[57,1] 207[58,1] 208[59,1] 209[60,1] 210[61,1] 211[62,1] 212[63,1] 213[64,1]
214[65,1] 215[66,1] 216[67,2] 217[69,1] 218[70,2] 219[72,1] 220[73,1] 221[74,1]
222[75,1] 223[76,1] 224[77,1] 225[78,1] 226[79,1] 227[80,1] 228[81,2] 229[83,1]
231[84,1] 232[85,1] 233[86,1] 234[87,1] 235[88,1] 236[89,1] 237[90,1] 238[91,1]
239[92,2] 240[94,1] 242[95,1] 243[96,1] 244[97,1] 245[98,1] 246[99,1]
247[100,1] 248[101,1] 249[102,1] 250[103,2] 251[105,1] 253[106,1] 254[107,1]
255[108,1] 256[109,1] 257[110,1] 258[111,1] 259[112,1] 260[113,1] 261[114,2]
262[116,1] 264[117,1] 265[118,1] 266[119,1] 267[120,1] 268[121,1] 269[122,1]
270[123,1] 271[124,1] 272[125,2] 273[127,1] 275[128,1] 276[129,1] 277[130,1]
278[131,1] 279[132,1] 280[133,1] 281[134,1] 282[135,1] 283[136,1] 284[137,2]
285[139,1] 287[140,1] 288[141,1] 289[142,1] 290[143,1] 291[144,1] 292[145,1]
293[146,1] 294[147,1] 295[148,1] 296[149,2] 297[151,1] 299[152,1] 300[153,1]
301[154,1] 302[155,1] 303[156,1] 304[157,1] 305[158,1] 306[159,1] 307[160,1]
308[161,2] 309[163,1] 311[164,1] 313[165,1] 315[166,1] 319[167,1]
( 2 5 )->[3]->( 5 4 )
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u14(1){ }u15(31){ }u16(67){ }u17(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
334 335 336 337 338 339
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
334 335 336 337 338 339
;; lr def 144 146 147 148 149 150 151 152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 178 179 180
181 182 183 184 185 186 187 188 190 192 195 196 197 198 199 200 201 202 203 204
205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
225 226 227 228 229 231 232 233 234 235 236 237 238 239 240 242 243 244 245 246
247 248 249 250 251 253 254 255 256 257 258 259 260 261 262 264 265 266 267 268
269 270 271 272 273 275 276 277 278 279 280 281 282 283 284 285 287 288 289 290
291 292 293 294 295 296 297 299 300 301 302 303 304 305 306 307 308 309 311 313
315 319
;; live in 180 181 182 183 184 185 186 187 319
;; live gen 144 146 147 148 149 150 151 152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 178 179 180
181 182 183 184 185 186 187 188 190 192 195 196 197 198 199 200 201 202 203 204
205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
225 226 227 228 229 231 232 233 234 235 236 237 238 239 240 242 243 244 245 246
247 248 249 250 251 253 254 255 256 257 258 259 260 261 262 264 265 266 267 268
269 270 271 272 273 275 276 277 278 279 280 281 282 283 284 285 287 288 289 290
291 292 293 294 295 296 297 299 300 301 302 303 304 305 306 307 308 309 311 313
315 319
;; live kill
;; rd in (157)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62,
63, 64, 65, 66, 68, 69, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 82, 83, 84, 85,
86, 87, 88, 89, 90, 91, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 104, 105,
106, 107, 108, 109, 110, 111, 112, 113, 115, 116, 117, 118, 119, 120, 121, 122,
123, 124, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 138, 139, 140,
141, 142, 143, 144, 145, 146, 147, 148, 150, 151, 152, 153, 154, 155, 156, 157,
158, 159, 160, 162, 163, 164, 165, 166, 167
;; rd gen (157)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62,
63, 64, 65, 66, 68, 69, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 82, 83, 84, 85,
86, 87, 88, 89, 90, 91, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 104, 105,
106, 107, 108, 109, 110, 111, 112, 113, 115, 116, 117, 118, 119, 120, 121, 122,
123, 124, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 138, 139, 140,
141, 142, 143, 144, 145, 146, 147, 148, 150, 151, 152, 153, 154, 155, 156, 157,
158, 159, 160, 162, 163, 164, 165, 166, 167
;; rd kill (168)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,
82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100,
101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116,
117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132,
133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148,
149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164,
165, 166, 167
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
334 335 336 337 338 339
;; live out 180 181 182 183 184 185 186 187 319
;; rd out (157)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62,
63, 64, 65, 66, 68, 69, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 82, 83, 84, 85,
86, 87, 88, 89, 90, 91, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 104, 105,
106, 107, 108, 109, 110, 111, 112, 113, 115, 116, 117, 118, 119, 120, 121, 122,
123, 124, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 138, 139, 140,
141, 142, 143, 144, 145, 146, 147, 148, 150, 151, 152, 153, 154, 155, 156, 157,
158, 159, 160, 162, 163, 164, 165, 166, 167
;; UD chains for artificial uses
;; reg 1 { }
;; reg 31 { }
;; reg 67 { }
;; reg 113 { }
;; UD chains for insn luid 0 uid 47
;; reg 187 { d41(bb 3 insn 253) }
;; UD chains for insn luid 1 uid 49
;; reg 185 { d39(bb 3 insn 255) }
;; UD chains for insn luid 2 uid 51
;; reg 317 { }
;; UD chains for insn luid 3 uid 52
;; reg 189 { }
;; UD chains for insn luid 4 uid 53
;; reg 189 { }
;; UD chains for insn luid 5 uid 54
;; reg 195 { d45(bb 3 insn 51) }
;; reg 197 { d47(bb 3 insn 52) }
;; reg 198 { d48(bb 3 insn 53) }
;; UD chains for insn luid 6 uid 55
;; reg 113 { }
;; reg 196 { d46(bb 3 insn 54) }
;; UD chains for insn luid 7 uid 56
;; reg 113 { }
;; UD chains for insn luid 8 uid 57
;; reg 192 { d44(bb 3 insn 47) }
;; UD chains for insn luid 9 uid 58
;; reg 199 { d49(bb 3 insn 57) }
;; UD chains for insn luid 10 uid 59
;; reg 192 { d44(bb 3 insn 47) }
;; UD chains for insn luid 11 uid 60
;; reg 190 { d43(bb 3 insn 49) }
;; reg 200 { d50(bb 3 insn 58) }
;; reg 202 { d52(bb 3 insn 59) }
;; UD chains for insn luid 12 uid 61
;; reg 113 { }
;; reg 179 { d33(bb 3 insn 56) }
;; UD chains for insn luid 13 uid 62
;; reg 113 { }
;; UD chains for insn luid 14 uid 63
;; reg 203 { d53(bb 3 insn 62) }
;; UD chains for insn luid 15 uid 65
;; reg 319 { d167(bb 3 insn 312) }
;; reg 319 { d167(bb 3 insn 312) }
;; UD chains for insn luid 16 uid 66
;; reg 201 { d51(bb 3 insn 60) }
;; reg 203 { d54(bb 3 insn 63) }
;; reg 205 { d56(bb 3 insn 65) }
;; eq_note reg 201 { d51(bb 3 insn 60) }
;; eq_note reg 203 { d54(bb 3 insn 63) }
;; UD chains for insn luid 17 uid 292
;; reg 320 { }
;; UD chains for insn luid 18 uid 68
;; reg 204 { d55(bb 3 insn 66) }
;; reg 320 { }
;; eq_note reg 204 { d55(bb 3 insn 66) }
;; UD chains for insn luid 19 uid 69
;; reg 187 { d41(bb 3 insn 253) }
;; UD chains for insn luid 20 uid 72
;; reg 187 { d41(bb 3 insn 253) }
;; UD chains for insn luid 21 uid 293
;; reg 321 { }
;; UD chains for insn luid 22 uid 74
;; reg 321 { }
;; UD chains for insn luid 23 uid 75
;; reg 316 { }
;; UD chains for insn luid 24 uid 76
;; reg 316 { }
;; UD chains for insn luid 25 uid 77
;; reg 208 { d59(bb 3 insn 74) }
;; reg 210 { d61(bb 3 insn 75) }
;; reg 211 { d62(bb 3 insn 76) }
;; UD chains for insn luid 26 uid 78
;; reg 113 { }
;; reg 209 { d60(bb 3 insn 77) }
;; UD chains for insn luid 27 uid 79
;; reg 113 { }
;; UD chains for insn luid 28 uid 80
;; reg 146 { d1(bb 3 insn 69) }
;; UD chains for insn luid 29 uid 81
;; reg 212 { d63(bb 3 insn 80) }
;; UD chains for insn luid 30 uid 82
;; reg 146 { d1(bb 3 insn 69) }
;; UD chains for insn luid 31 uid 83
;; reg 176 { d31(bb 3 insn 72) }
;; reg 213 { d64(bb 3 insn 81) }
;; reg 215 { d66(bb 3 insn 82) }
;; UD chains for insn luid 32 uid 84
;; reg 113 { }
;; reg 175 { d30(bb 3 insn 79) }
;; UD chains for insn luid 33 uid 85
;; reg 113 { }
;; UD chains for insn luid 34 uid 86
;; reg 216 { d67(bb 3 insn 85) }
;; UD chains for insn luid 35 uid 294
;; reg 322 { }
;; UD chains for insn luid 36 uid 295
;; reg 323 { }
;; UD chains for insn luid 37 uid 89
;; reg 214 { d65(bb 3 insn 83) }
;; reg 216 { d68(bb 3 insn 86) }
;; reg 323 { }
;; eq_note reg 214 { d65(bb 3 insn 83) }
;; eq_note reg 216 { d68(bb 3 insn 86) }
;; UD chains for insn luid 38 uid 90
;; reg 178 { d32(bb 3 insn 68) }
;; reg 217 { d69(bb 3 insn 89) }
;; UD chains for insn luid 39 uid 91
;; reg 187 { d41(bb 3 insn 253) }
;; UD chains for insn luid 40 uid 296
;; reg 324 { }
;; UD chains for insn luid 41 uid 94
;; reg 184 { d38(bb 3 insn 256) }
;; UD chains for insn luid 42 uid 297
;; reg 325 { }
;; UD chains for insn luid 43 uid 96
;; reg 325 { }
;; UD chains for insn luid 44 uid 97
;; reg 324 { }
;; UD chains for insn luid 45 uid 98
;; reg 324 { }
;; UD chains for insn luid 46 uid 99
;; reg 220 { d73(bb 3 insn 96) }
;; reg 222 { d75(bb 3 insn 97) }
;; reg 223 { d76(bb 3 insn 98) }
;; UD chains for insn luid 47 uid 100
;; reg 113 { }
;; reg 221 { d74(bb 3 insn 99) }
;; UD chains for insn luid 48 uid 101
;; reg 113 { }
;; UD chains for insn luid 49 uid 102
;; reg 144 { d0(bb 3 insn 91) }
;; UD chains for insn luid 50 uid 103
;; reg 224 { d77(bb 3 insn 102) }
;; UD chains for insn luid 51 uid 104
;; reg 144 { d0(bb 3 insn 91) }
;; UD chains for insn luid 52 uid 105
;; reg 172 { d27(bb 3 insn 94) }
;; reg 225 { d78(bb 3 insn 103) }
;; reg 227 { d80(bb 3 insn 104) }
;; UD chains for insn luid 53 uid 106
;; reg 113 { }
;; reg 171 { d26(bb 3 insn 101) }
;; UD chains for insn luid 54 uid 107
;; reg 113 { }
;; UD chains for insn luid 55 uid 108
;; reg 228 { d81(bb 3 insn 107) }
;; UD chains for insn luid 56 uid 111
;; reg 226 { d79(bb 3 insn 105) }
;; reg 228 { d82(bb 3 insn 108) }
;; reg 323 { }
;; eq_note reg 226 { d79(bb 3 insn 105) }
;; eq_note reg 228 { d82(bb 3 insn 108) }
;; UD chains for insn luid 57 uid 112
;; reg 174 { d29(bb 3 insn 90) }
;; reg 229 { d83(bb 3 insn 111) }
;; UD chains for insn luid 58 uid 298
;; reg 326 { }
;; UD chains for insn luid 59 uid 115
;; reg 183 { d37(bb 3 insn 257) }
;; UD chains for insn luid 60 uid 299
;; reg 327 { }
;; UD chains for insn luid 61 uid 117
;; reg 327 { }
;; UD chains for insn luid 62 uid 118
;; reg 326 { }
;; UD chains for insn luid 63 uid 119
;; reg 326 { }
;; UD chains for insn luid 64 uid 120
;; reg 232 { d85(bb 3 insn 117) }
;; reg 234 { d87(bb 3 insn 118) }
;; reg 235 { d88(bb 3 insn 119) }
;; UD chains for insn luid 65 uid 121
;; reg 113 { }
;; reg 233 { d86(bb 3 insn 120) }
;; UD chains for insn luid 66 uid 122
;; reg 113 { }
;; UD chains for insn luid 67 uid 123
;; reg 185 { d39(bb 3 insn 255) }
;; UD chains for insn luid 68 uid 124
;; reg 236 { d89(bb 3 insn 123) }
;; UD chains for insn luid 69 uid 125
;; reg 168 { d23(bb 3 insn 115) }
;; reg 190 { d43(bb 3 insn 49) }
;; reg 237 { d90(bb 3 insn 124) }
;; UD chains for insn luid 70 uid 126
;; reg 113 { }
;; reg 167 { d22(bb 3 insn 122) }
;; UD chains for insn luid 71 uid 127
;; reg 113 { }
;; UD chains for insn luid 72 uid 128
;; reg 239 { d92(bb 3 insn 127) }
;; UD chains for insn luid 73 uid 131
;; reg 238 { d91(bb 3 insn 125) }
;; reg 239 { d93(bb 3 insn 128) }
;; reg 323 { }
;; eq_note reg 238 { d91(bb 3 insn 125) }
;; eq_note reg 239 { d93(bb 3 insn 128) }
;; UD chains for insn luid 74 uid 132
;; reg 170 { d25(bb 3 insn 112) }
;; reg 240 { d94(bb 3 insn 131) }
;; UD chains for insn luid 75 uid 300
;; reg 328 { }
;; UD chains for insn luid 76 uid 135
;; reg 182 { d36(bb 3 insn 258) }
;; UD chains for insn luid 77 uid 301
;; reg 329 { }
;; UD chains for insn luid 78 uid 137
;; reg 329 { }
;; UD chains for insn luid 79 uid 138
;; reg 328 { }
;; UD chains for insn luid 80 uid 139
;; reg 328 { }
;; UD chains for insn luid 81 uid 140
;; reg 243 { d96(bb 3 insn 137) }
;; reg 245 { d98(bb 3 insn 138) }
;; reg 246 { d99(bb 3 insn 139) }
;; UD chains for insn luid 82 uid 141
;; reg 113 { }
;; reg 244 { d97(bb 3 insn 140) }
;; UD chains for insn luid 83 uid 142
;; reg 113 { }
;; UD chains for insn luid 84 uid 143
;; reg 187 { d41(bb 3 insn 253) }
;; UD chains for insn luid 85 uid 144
;; reg 247 { d100(bb 3 insn 143) }
;; UD chains for insn luid 86 uid 145
;; reg 164 { d19(bb 3 insn 135) }
;; reg 176 { d31(bb 3 insn 72) }
;; reg 248 { d101(bb 3 insn 144) }
;; UD chains for insn luid 87 uid 146
;; reg 113 { }
;; reg 163 { d18(bb 3 insn 142) }
;; UD chains for insn luid 88 uid 147
;; reg 113 { }
;; UD chains for insn luid 89 uid 148
;; reg 250 { d103(bb 3 insn 147) }
;; UD chains for insn luid 90 uid 151
;; reg 249 { d102(bb 3 insn 145) }
;; reg 250 { d104(bb 3 insn 148) }
;; reg 323 { }
;; eq_note reg 249 { d102(bb 3 insn 145) }
;; eq_note reg 250 { d104(bb 3 insn 148) }
;; UD chains for insn luid 91 uid 152
;; reg 166 { d21(bb 3 insn 132) }
;; reg 251 { d105(bb 3 insn 151) }
;; UD chains for insn luid 92 uid 302
;; reg 330 { }
;; UD chains for insn luid 93 uid 155
;; reg 181 { d35(bb 3 insn 259) }
;; UD chains for insn luid 94 uid 303
;; reg 331 { }
;; UD chains for insn luid 95 uid 157
;; reg 331 { }
;; UD chains for insn luid 96 uid 158
;; reg 330 { }
;; UD chains for insn luid 97 uid 159
;; reg 330 { }
;; UD chains for insn luid 98 uid 160
;; reg 254 { d107(bb 3 insn 157) }
;; reg 256 { d109(bb 3 insn 158) }
;; reg 257 { d110(bb 3 insn 159) }
;; UD chains for insn luid 99 uid 161
;; reg 113 { }
;; reg 255 { d108(bb 3 insn 160) }
;; UD chains for insn luid 100 uid 162
;; reg 113 { }
;; UD chains for insn luid 101 uid 163
;; reg 184 { d38(bb 3 insn 256) }
;; UD chains for insn luid 102 uid 164
;; reg 258 { d111(bb 3 insn 163) }
;; UD chains for insn luid 103 uid 165
;; reg 160 { d15(bb 3 insn 155) }
;; reg 172 { d27(bb 3 insn 94) }
;; reg 259 { d112(bb 3 insn 164) }
;; UD chains for insn luid 104 uid 166
;; reg 113 { }
;; reg 159 { d14(bb 3 insn 162) }
;; UD chains for insn luid 105 uid 167
;; reg 113 { }
;; UD chains for insn luid 106 uid 168
;; reg 261 { d114(bb 3 insn 167) }
;; UD chains for insn luid 107 uid 171
;; reg 260 { d113(bb 3 insn 165) }
;; reg 261 { d115(bb 3 insn 168) }
;; reg 323 { }
;; eq_note reg 260 { d113(bb 3 insn 165) }
;; eq_note reg 261 { d115(bb 3 insn 168) }
;; UD chains for insn luid 108 uid 172
;; reg 162 { d17(bb 3 insn 152) }
;; reg 262 { d116(bb 3 insn 171) }
;; UD chains for insn luid 109 uid 304
;; reg 332 { }
;; UD chains for insn luid 110 uid 175
;; reg 180 { d34(bb 3 insn 260) }
;; UD chains for insn luid 111 uid 305
;; reg 333 { }
;; UD chains for insn luid 112 uid 177
;; reg 333 { }
;; UD chains for insn luid 113 uid 178
;; reg 332 { }
;; UD chains for insn luid 114 uid 179
;; reg 332 { }
;; UD chains for insn luid 115 uid 180
;; reg 265 { d118(bb 3 insn 177) }
;; reg 267 { d120(bb 3 insn 178) }
;; reg 268 { d121(bb 3 insn 179) }
;; UD chains for insn luid 116 uid 181
;; reg 113 { }
;; reg 266 { d119(bb 3 insn 180) }
;; UD chains for insn luid 117 uid 182
;; reg 113 { }
;; UD chains for insn luid 118 uid 183
;; reg 183 { d37(bb 3 insn 257) }
;; UD chains for insn luid 119 uid 184
;; reg 269 { d122(bb 3 insn 183) }
;; UD chains for insn luid 120 uid 185
;; reg 156 { d11(bb 3 insn 175) }
;; reg 168 { d23(bb 3 insn 115) }
;; reg 270 { d123(bb 3 insn 184) }
;; UD chains for insn luid 121 uid 186
;; reg 113 { }
;; reg 155 { d10(bb 3 insn 182) }
;; UD chains for insn luid 122 uid 187
;; reg 113 { }
;; UD chains for insn luid 123 uid 188
;; reg 272 { d125(bb 3 insn 187) }
;; UD chains for insn luid 124 uid 191
;; reg 271 { d124(bb 3 insn 185) }
;; reg 272 { d126(bb 3 insn 188) }
;; reg 323 { }
;; eq_note reg 271 { d124(bb 3 insn 185) }
;; eq_note reg 272 { d126(bb 3 insn 188) }
;; UD chains for insn luid 125 uid 192
;; reg 158 { d13(bb 3 insn 172) }
;; reg 273 { d127(bb 3 insn 191) }
;; UD chains for insn luid 126 uid 306
;; reg 334 { }
;; UD chains for insn luid 127 uid 307
;; reg 335 { }
;; UD chains for insn luid 128 uid 195
;; reg 335 { }
;; UD chains for insn luid 129 uid 196
;; reg 334 { }
;; UD chains for insn luid 130 uid 197
;; reg 334 { }
;; UD chains for insn luid 131 uid 198
;; reg 276 { d129(bb 3 insn 195) }
;; reg 278 { d131(bb 3 insn 196) }
;; reg 279 { d132(bb 3 insn 197) }
;; UD chains for insn luid 132 uid 199
;; reg 113 { }
;; reg 277 { d130(bb 3 insn 198) }
;; UD chains for insn luid 133 uid 200
;; reg 113 { }
;; UD chains for insn luid 134 uid 201
;; reg 182 { d36(bb 3 insn 258) }
;; UD chains for insn luid 135 uid 202
;; reg 280 { d133(bb 3 insn 201) }
;; UD chains for insn luid 136 uid 203
;; reg 187 { d41(bb 3 insn 253) }
;; UD chains for insn luid 137 uid 204
;; reg 164 { d19(bb 3 insn 135) }
;; reg 281 { d134(bb 3 insn 202) }
;; reg 283 { d136(bb 3 insn 203) }
;; UD chains for insn luid 138 uid 205
;; reg 113 { }
;; reg 152 { d7(bb 3 insn 200) }
;; UD chains for insn luid 139 uid 206
;; reg 113 { }
;; UD chains for insn luid 140 uid 207
;; reg 284 { d137(bb 3 insn 206) }
;; UD chains for insn luid 141 uid 210
;; reg 282 { d135(bb 3 insn 204) }
;; reg 284 { d138(bb 3 insn 207) }
;; reg 323 { }
;; eq_note reg 282 { d135(bb 3 insn 204) }
;; eq_note reg 284 { d138(bb 3 insn 207) }
;; UD chains for insn luid 142 uid 211
;; reg 154 { d9(bb 3 insn 192) }
;; reg 285 { d139(bb 3 insn 210) }
;; UD chains for insn luid 143 uid 308
;; reg 336 { }
;; UD chains for insn luid 144 uid 309
;; reg 337 { }
;; UD chains for insn luid 145 uid 214
;; reg 337 { }
;; UD chains for insn luid 146 uid 215
;; reg 336 { }
;; UD chains for insn luid 147 uid 216
;; reg 336 { }
;; UD chains for insn luid 148 uid 217
;; reg 288 { d141(bb 3 insn 214) }
;; reg 290 { d143(bb 3 insn 215) }
;; reg 291 { d144(bb 3 insn 216) }
;; UD chains for insn luid 149 uid 218
;; reg 113 { }
;; reg 289 { d142(bb 3 insn 217) }
;; UD chains for insn luid 150 uid 219
;; reg 113 { }
;; UD chains for insn luid 151 uid 220
;; reg 181 { d35(bb 3 insn 259) }
;; UD chains for insn luid 152 uid 221
;; reg 292 { d145(bb 3 insn 220) }
;; UD chains for insn luid 153 uid 222
;; reg 187 { d41(bb 3 insn 253) }
;; UD chains for insn luid 154 uid 223
;; reg 160 { d15(bb 3 insn 155) }
;; reg 293 { d146(bb 3 insn 221) }
;; reg 295 { d148(bb 3 insn 222) }
;; UD chains for insn luid 155 uid 224
;; reg 113 { }
;; reg 149 { d4(bb 3 insn 219) }
;; UD chains for insn luid 156 uid 225
;; reg 113 { }
;; UD chains for insn luid 157 uid 226
;; reg 296 { d149(bb 3 insn 225) }
;; UD chains for insn luid 158 uid 229
;; reg 294 { d147(bb 3 insn 223) }
;; reg 296 { d150(bb 3 insn 226) }
;; reg 323 { }
;; eq_note reg 294 { d147(bb 3 insn 223) }
;; eq_note reg 296 { d150(bb 3 insn 226) }
;; UD chains for insn luid 159 uid 230
;; reg 151 { d6(bb 3 insn 211) }
;; reg 297 { d151(bb 3 insn 229) }
;; UD chains for insn luid 160 uid 310
;; reg 338 { }
;; UD chains for insn luid 161 uid 311
;; reg 339 { }
;; UD chains for insn luid 162 uid 233
;; reg 339 { }
;; UD chains for insn luid 163 uid 234
;; reg 338 { }
;; UD chains for insn luid 164 uid 235
;; reg 338 { }
;; UD chains for insn luid 165 uid 236
;; reg 300 { d153(bb 3 insn 233) }
;; reg 302 { d155(bb 3 insn 234) }
;; reg 303 { d156(bb 3 insn 235) }
;; UD chains for insn luid 166 uid 237
;; reg 113 { }
;; reg 301 { d154(bb 3 insn 236) }
;; UD chains for insn luid 167 uid 238
;; reg 113 { }
;; UD chains for insn luid 168 uid 239
;; reg 180 { d34(bb 3 insn 260) }
;; UD chains for insn luid 169 uid 240
;; reg 304 { d157(bb 3 insn 239) }
;; UD chains for insn luid 170 uid 241
;; reg 187 { d41(bb 3 insn 253) }
;; UD chains for insn luid 171 uid 242
;; reg 156 { d11(bb 3 insn 175) }
;; reg 305 { d158(bb 3 insn 240) }
;; reg 307 { d160(bb 3 insn 241) }
;; UD chains for insn luid 172 uid 243
;; reg 113 { }
;; reg 188 { d42(bb 3 insn 238) }
;; UD chains for insn luid 173 uid 244
;; reg 113 { }
;; UD chains for insn luid 174 uid 245
;; reg 308 { d161(bb 3 insn 244) }
;; UD chains for insn luid 175 uid 312
;; reg 322 { }
;; UD chains for insn luid 176 uid 248
;; reg 306 { d159(bb 3 insn 242) }
;; reg 308 { d162(bb 3 insn 245) }
;; reg 323 { }
;; eq_note reg 306 { d159(bb 3 insn 242) }
;; eq_note reg 308 { d162(bb 3 insn 245) }
;; UD chains for insn luid 177 uid 249
;; reg 148 { d3(bb 3 insn 230) }
;; reg 309 { d163(bb 3 insn 248) }
;; UD chains for insn luid 178 uid 251
;; reg 311 { d164(bb 3 insn 249) }
;; reg 320 { }
;; eq_note reg 311 { d164(bb 3 insn 249) }
;; UD chains for insn luid 179 uid 252
;; reg 186 { d40(bb 3 insn 254) }
;; reg 313 { d165(bb 3 insn 251) }
;; UD chains for insn luid 180 uid 253
;; reg 187 { d41(bb 3 insn 253) }
;; UD chains for insn luid 181 uid 254
;; reg 186 { d40(bb 3 insn 254) }
;; UD chains for insn luid 182 uid 255
;; reg 185 { d39(bb 3 insn 255) }
;; UD chains for insn luid 183 uid 256
;; reg 184 { d38(bb 3 insn 256) }
;; UD chains for insn luid 184 uid 257
;; reg 183 { d37(bb 3 insn 257) }
;; UD chains for insn luid 185 uid 258
;; reg 182 { d36(bb 3 insn 258) }
;; UD chains for insn luid 186 uid 259
;; reg 181 { d35(bb 3 insn 259) }
;; UD chains for insn luid 187 uid 260
;; reg 180 { d34(bb 3 insn 260) }
;; UD chains for insn luid 189 uid 264
;; reg 186 { d40(bb 3 insn 254) }
;; reg 318 { }
;; eq_note reg 186 { d40(bb 3 insn 254) }
;; UD chains for insn luid 190 uid 265
;; reg 315 { d166(bb 3 insn 264) }
( 3 )->[5]->( 3 )
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u-1(1){ }u-1(31){ }u-1(67){ }u-1(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
334 335 336 337 338 339
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def
;; live in 180 181 182 183 184 185 186 187 319
;; live gen
;; live kill
;; rd in (157)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62,
63, 64, 65, 66, 68, 69, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 82, 83, 84, 85,
86, 87, 88, 89, 90, 91, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 104, 105,
106, 107, 108, 109, 110, 111, 112, 113, 115, 116, 117, 118, 119, 120, 121, 122,
123, 124, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 138, 139, 140,
141, 142, 143, 144, 145, 146, 147, 148, 150, 151, 152, 153, 154, 155, 156, 157,
158, 159, 160, 162, 163, 164, 165, 166, 167
;; rd gen (0)
;; rd kill (0)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
334 335 336 337 338 339
;; live out 180 181 182 183 184 185 186 187 319
;; rd out (157)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62,
63, 64, 65, 66, 68, 69, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 82, 83, 84, 85,
86, 87, 88, 89, 90, 91, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 104, 105,
106, 107, 108, 109, 110, 111, 112, 113, 115, 116, 117, 118, 119, 120, 121, 122,
123, 124, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 138, 139, 140,
141, 142, 143, 144, 145, 146, 147, 148, 150, 151, 152, 153, 154, 155, 156, 157,
158, 159, 160, 162, 163, 164, 165, 166, 167
;; UD chains for artificial uses
;; reg 1 { }
;; reg 31 { }
;; reg 67 { }
;; reg 113 { }
Analyzing operand (reg:DI 186 [ ivtmp.59 ]) of insn (insn 264 262 265 3
vect-outer-fir2-kernel.c:47 (set (reg:CC 315)
(compare:CC (reg:DI 186 [ ivtmp.59 ])
(reg/f:DI 318))) 459 {*cmpdi_internal1} (expr_list:REG_EQUAL
(compare:CC (reg:DI 186 [ ivtmp.59 ])
(const:DI (plus:DI (symbol_ref:DI ("fir_out") [flags 0x80]
<var_decl 0xf7d571c0 fir_out>)
(const_int 160 [0xa0]))))
(nil)))
Analyzing def of (reg:DI 186 [ ivtmp.59 ]) in insn (insn 254 253 255 3
vect-outer-fir2-kernel.c:47 (set (reg:DI 186 [ ivtmp.59 ])
(plus:DI (reg:DI 186 [ ivtmp.59 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
Analyzing operand (reg:DI 186 [ ivtmp.59 ]) of insn (insn 254 253 255 3
vect-outer-fir2-kernel.c:47 (set (reg:DI 186 [ ivtmp.59 ])
(plus:DI (reg:DI 186 [ ivtmp.59 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
Analyzing (reg:DI 186 [ ivtmp.59 ]) for bivness.
not simple.
(reg:DI 186 [ ivtmp.59 ]) in insn (insn 254 253 255 3
vect-outer-fir2-kernel.c:47 (set (reg:DI 186 [ ivtmp.59 ])
(plus:DI (reg:DI 186 [ ivtmp.59 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
is not simple
Loop 1 is not simple.
;; Unable to prove that the loop rolls exactly once
;; Considering peeling completely
;; Unable to prove that the loop iterates constant times
;; *** Considering loop 1 ***
;; Considering unrolling loop with constant number of iterations
;; Not considering loop, is too big
;; Considering unrolling loop with runtime computable number of iterations
;; Not considering loop, is too big
starting the processing of deferred insns
ending the processing of deferred insns
fir
Dataflow summary:
;; invalidated by call 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9
[9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5]
38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [mq] 65 [lr] 66
[ctr] 68 [0] 69 [1] 73 [5] 74 [6] 75 [7] 76 [xer] 77 [0] 78 [1] 79 [2] 80 [3]
81 [4] 82 [5] 83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 91
[14] 92 [15] 93 [16] 94 [17] 95 [18] 96 [19] 110 [vscr]
;; hardware regs used 1 [1] 67 [ap] 113 [sfp]
;; regular block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; eh block artificial uses 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; entry block defs 1 [1] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10
[10] 11 [11] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41
[9] 42 [10] 43 [11] 44 [12] 45 [13] 65 [lr] 67 [ap] 79 [2] 80 [3] 81 [4] 82 [5]
83 [6] 84 [7] 85 [8] 86 [9] 87 [10] 88 [11] 89 [12] 90 [13] 113 [sfp]
;; exit block uses 1 [1] 31 [31] 109 [vrsave] 110 [vscr] 113 [sfp]
;; regs ever live 2[2]
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(1){ }u1(31){ }u2(67){ }u3(113){ }}
;; lr in 1 [1] 2 [2] 31 [31] 67 [ap] 109 [vrsave] 110 [vscr] 113 [sfp]
;; lr use 1 [1] 2 [2] 31 [31] 67 [ap] 113 [sfp]
;; lr def 180 181 182 183 184 185 186 187 189 193 316 317 318 319 320
321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen 180 181 182 183 184 185 186 187 189 193 316 317 318 319 320
321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339
;; live kill
;; Pred edge ENTRY [100.0%] (fallthru)
(note 31 0 30 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 30 31 33 2 NOTE_INSN_FUNCTION_BEG)
(insn 33 30 34 2 vect-outer-fir2-kernel.c:38 (use (symbol_ref:DI ("in") [flags
0x80] <var_decl 0xf7d45d90 in>)) -1 (nil))
(insn 34 33 35 2 vect-outer-fir2-kernel.c:38 (set (reg/f:DI 193 [ vect_pin.20
])
(mem/u/c:DI (plus:DI (reg:DI 2 2)
(const:DI (minus:DI (symbol_ref/u:DI ("*.LC2") [flags 0x2])
(symbol_ref:DI ("*.LCTOC1"))))) [7 S8 A8])) 344
{*movdi_internal64} (expr_list:REG_EQUAL (symbol_ref:DI ("in") [flags 0x80]
<var_decl 0xf7d45d90 in>)
(nil)))
(insn 35 34 36 2 vect-outer-fir2-kernel.c:38 (use (symbol_ref:DI ("coeff")
[flags 0x80] <var_decl 0xf7d45ee0 coeff>)) -1 (nil))
(insn 36 35 37 2 vect-outer-fir2-kernel.c:38 (set (reg/f:DI 189 [ ivtmp.33 ])
(mem/u/c:DI (plus:DI (reg:DI 2 2)
(const:DI (minus:DI (symbol_ref/u:DI ("*.LC3") [flags 0x2])
(symbol_ref:DI ("*.LCTOC1"))))) [7 S8 A8])) 344
{*movdi_internal64} (expr_list:REG_EQUAL (symbol_ref:DI ("coeff") [flags 0x80]
<var_decl 0xf7d45ee0 coeff>)
(nil)))
(insn 37 36 38 2 vect-outer-fir2-kernel.c:38 (set (reg:DI 187 [ ivtmp.58 ])
(plus:DI (reg/f:DI 193 [ vect_pin.20 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("in") [flags 0x80] <var_decl 0xf7d45d90 in>)
(const_int 16 [0x10])))
(nil)))
(insn 38 37 39 2 vect-outer-fir2-kernel.c:38 (use (symbol_ref:DI ("fir_out")
[flags 0x80] <var_decl 0xf7d571c0 fir_out>)) -1 (nil))
(insn 39 38 40 2 vect-outer-fir2-kernel.c:38 (set (reg:DI 186 [ ivtmp.59 ])
(mem/u/c:DI (plus:DI (reg:DI 2 2)
(const:DI (minus:DI (symbol_ref/u:DI ("*.LC4") [flags 0x2])
(symbol_ref:DI ("*.LCTOC1"))))) [7 S8 A8])) 344
{*movdi_internal64} (expr_list:REG_EQUAL (symbol_ref:DI ("fir_out") [flags
0x80] <var_decl 0xf7d571c0 fir_out>)
(nil)))
(insn 40 39 41 2 vect-outer-fir2-kernel.c:38 (set (reg:DI 185 [ ivtmp.62 ])
(plus:DI (reg/f:DI 193 [ vect_pin.20 ])
(const_int 12 [0xc]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("in") [flags 0x80] <var_decl 0xf7d45d90 in>)
(const_int 12 [0xc])))
(nil)))
(insn 41 40 42 2 vect-outer-fir2-kernel.c:38 (set (reg:DI 184 [ ivtmp.65 ])
(plus:DI (reg/f:DI 193 [ vect_pin.20 ])
(const_int 20 [0x14]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("in") [flags 0x80] <var_decl 0xf7d45d90 in>)
(const_int 20 [0x14])))
(nil)))
(insn 42 41 43 2 vect-outer-fir2-kernel.c:38 (set (reg:DI 183 [ ivtmp.66 ])
(plus:DI (reg/f:DI 193 [ vect_pin.20 ])
(const_int 24 [0x18]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("in") [flags 0x80] <var_decl 0xf7d45d90 in>)
(const_int 24 [0x18])))
(nil)))
(insn 43 42 44 2 vect-outer-fir2-kernel.c:38 (set (reg:DI 182 [ ivtmp.67 ])
(plus:DI (reg/f:DI 193 [ vect_pin.20 ])
(const_int 28 [0x1c]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("in") [flags 0x80] <var_decl 0xf7d45d90 in>)
(const_int 28 [0x1c])))
(nil)))
(insn 44 43 45 2 vect-outer-fir2-kernel.c:38 (set (reg:DI 181 [ ivtmp.68 ])
(plus:DI (reg/f:DI 193 [ vect_pin.20 ])
(const_int 32 [0x20]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("in") [flags 0x80] <var_decl 0xf7d45d90 in>)
(const_int 32 [0x20])))
(nil)))
(insn 45 44 283 2 vect-outer-fir2-kernel.c:38 (set (reg:DI 180 [ ivtmp.69 ])
(plus:DI (reg/f:DI 193 [ vect_pin.20 ])
(const_int 36 [0x24]))) 80 {*adddi3_internal1} (expr_list:REG_DEAD
(reg/f:DI 193 [ vect_pin.20 ])
(expr_list:REG_EQUAL (const:DI (plus:DI (symbol_ref:DI ("in") [flags
0x80] <var_decl 0xf7d45d90 in>)
(const_int 36 [0x24])))
(nil))))
(insn 283 45 284 2 (set (reg:DI 317)
(neg:DI (reg/f:DI 189 [ ivtmp.33 ]))) 103 {*negdi2_internal} (nil))
(insn 284 283 285 2 (set (reg:V4SI 319)
(vec_duplicate:V4SI (const_int -1 [0xffffffffffffffff]))) 794
{altivec_vspltisw} (expr_list:REG_EQUAL (const_vector:V4SI [
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
])
(nil)))
(insn 285 284 286 2 (use (const:DI (plus:DI (symbol_ref:DI ("coeff") [flags
0x80] <var_decl 0xf7d45ee0 coeff>)
(const_int 4 [0x4])))) -1 (nil))
(insn 286 285 287 2 (set (reg/f:DI 316)
(plus:DI (reg/f:DI 189 [ ivtmp.33 ])
(const_int 4 [0x4]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0
coeff>)
(const_int 4 [0x4])))
(nil)))
(insn 287 286 288 2 (use (const:DI (plus:DI (symbol_ref:DI ("fir_out") [flags
0x80] <var_decl 0xf7d571c0 fir_out>)
(const_int 160 [0xa0])))) -1 (nil))
(insn 288 287 67 2 (set (reg/f:DI 318)
(plus:DI (reg:DI 186 [ ivtmp.59 ])
(const_int 160 [0xa0]))) 80 {*adddi3_internal1} (expr_list:REG_DEAD
(reg:DI 2 2)
(expr_list:REG_EQUAL (const:DI (plus:DI (symbol_ref:DI ("fir_out")
[flags 0x80] <var_decl 0xf7d571c0 fir_out>)
(const_int 160 [0xa0])))
(nil))))
(insn 67 288 73 2 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 320)
(const_vector:V4SF [
(const_double:SF 0.0 [0x0.0p+0])
(const_double:SF 0.0 [0x0.0p+0])
(const_double:SF 0.0 [0x0.0p+0])
(const_double:SF 0.0 [0x0.0p+0])
])) 654 {*movv4sf_internal} (nil))
(insn 73 67 87 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 321)
(neg:DI (reg/f:DI 316))) 103 {*negdi2_internal} (expr_list:REG_EQUAL
(minus:DI (const_int -4 [0xfffffffffffffffc])
(symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0 coeff>))
(nil)))
(insn 87 73 88 2 vect-outer-fir2-kernel.c:45 (set (reg:V4SI 322)
(vec_duplicate:V4SI (const_int -1 [0xffffffffffffffff]))) 794
{altivec_vspltisw} (expr_list:REG_EQUAL (const_vector:V4SI [
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
])
(nil)))
(insn 88 87 92 2 vect-outer-fir2-kernel.c:45 (set (reg:V4SI 323)
(unspec:V4SI [
(reg:V4SI 322)
(reg:V4SI 322)
] 107)) 772 {altivec_vslw} (nil))
(insn 92 88 95 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 324)
(plus:DI (reg/f:DI 316)
(const_int 4 [0x4]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0
coeff>)
(const_int 8 [0x8])))
(nil)))
(insn 95 92 113 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 325)
(neg:DI (reg:DI 324))) 103 {*negdi2_internal} (nil))
(insn 113 95 116 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 326)
(plus:DI (reg:DI 324)
(const_int 4 [0x4]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0
coeff>)
(const_int 12 [0xc])))
(expr_list:REG_DEAD (reg/f:DI 173 [ ivtmp.107 ])
(nil))))
(insn 116 113 133 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 327)
(neg:DI (reg:DI 326))) 103 {*negdi2_internal} (nil))
(insn 133 116 136 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 328)
(plus:DI (reg:DI 326)
(const_int 4 [0x4]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0
coeff>)
(const_int 16 [0x10])))
(expr_list:REG_DEAD (reg/f:DI 169 [ ivtmp.121 ])
(nil))))
(insn 136 133 153 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 329)
(neg:DI (reg:DI 328))) 103 {*negdi2_internal} (nil))
(insn 153 136 156 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 330)
(plus:DI (reg:DI 328)
(const_int 4 [0x4]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0
coeff>)
(const_int 20 [0x14])))
(expr_list:REG_DEAD (reg/f:DI 165 [ ivtmp.134 ])
(nil))))
(insn 156 153 173 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 331)
(neg:DI (reg:DI 330))) 103 {*negdi2_internal} (nil))
(insn 173 156 176 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 332)
(plus:DI (reg:DI 330)
(const_int 4 [0x4]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0
coeff>)
(const_int 24 [0x18])))
(expr_list:REG_DEAD (reg/f:DI 161 [ ivtmp.147 ])
(nil))))
(insn 176 173 193 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 333)
(neg:DI (reg:DI 332))) 103 {*negdi2_internal} (nil))
(insn 193 176 194 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 334)
(plus:DI (reg:DI 332)
(const_int 4 [0x4]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0
coeff>)
(const_int 28 [0x1c])))
(expr_list:REG_DEAD (reg/f:DI 157 [ ivtmp.160 ])
(nil))))
(insn 194 193 212 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 335)
(neg:DI (reg:DI 334))) 103 {*negdi2_internal} (nil))
(insn 212 194 213 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 336)
(plus:DI (reg:DI 334)
(const_int 4 [0x4]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0
coeff>)
(const_int 32 [0x20])))
(expr_list:REG_DEAD (reg/f:DI 153 [ ivtmp.173 ])
(nil))))
(insn 213 212 231 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 337)
(neg:DI (reg:DI 336))) 103 {*negdi2_internal} (nil))
(insn 231 213 232 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 338)
(plus:DI (reg:DI 336)
(const_int 4 [0x4]))) 80 {*adddi3_internal1} (expr_list:REG_EQUAL
(const:DI (plus:DI (symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0
coeff>)
(const_int 36 [0x24])))
(expr_list:REG_DEAD (reg/f:DI 150 [ ivtmp.186 ])
(nil))))
(insn 232 231 261 2 vect-outer-fir2-kernel.c:45 (set (reg:DI 339)
(neg:DI (reg:DI 338))) 103 {*negdi2_internal} (nil))
;; End of basic block 2 -> ( 3)
;; lr out 1 [1] 31 [31] 67 [ap] 109 [vrsave] 110 [vscr] 113 [sfp] 180
181 182 183 184 185 186 187 189 316 317 318 319
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319
;; Succ edge 3 [100.0%] (fallthru)
;; Start of basic block ( 2 5) -> 3
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u14(1){ }u15(31){ }u16(67){ }u17(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
334 335 336 337 338 339
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
334 335 336 337 338 339
;; lr def 144 146 147 148 149 150 151 152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 178 179 180
181 182 183 184 185 186 187 188 190 192 195 196 197 198 199 200 201 202 203 204
205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
225 226 227 228 229 231 232 233 234 235 236 237 238 239 240 242 243 244 245 246
247 248 249 250 251 253 254 255 256 257 258 259 260 261 262 264 265 266 267 268
269 270 271 272 273 275 276 277 278 279 280 281 282 283 284 285 287 288 289 290
291 292 293 294 295 296 297 299 300 301 302 303 304 305 306 307 308 309 311 313
315 319
;; live in 180 181 182 183 184 185 186 187 319
;; live gen 144 146 147 148 149 150 151 152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 178 179 180
181 182 183 184 185 186 187 188 190 192 195 196 197 198 199 200 201 202 203 204
205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
225 226 227 228 229 231 232 233 234 235 236 237 238 239 240 242 243 244 245 246
247 248 249 250 251 253 254 255 256 257 258 259 260 261 262 264 265 266 267 268
269 270 271 272 273 275 276 277 278 279 280 281 282 283 284 285 287 288 289 290
291 292 293 294 295 296 297 299 300 301 302 303 304 305 306 307 308 309 311 313
315 319
;; live kill
;; Pred edge 2 [100.0%] (fallthru)
;; Pred edge 5 [100.0%] (fallthru)
(code_label 261 232 46 3 2 "" [0 uses])
(note 46 261 47 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 47 46 49 3 vect-outer-fir2-kernel.c:38 (set (reg:DI 192 [ ivtmp.21 ])
(plus:DI (reg:DI 187 [ ivtmp.58 ])
(const_int -16 [0xfffffffffffffff0]))) 80 {*adddi3_internal1}
(nil))
(insn 49 47 51 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 190 [ vect_var_.25
])
(mem:V4SF (and:DI (reg:DI 185 [ ivtmp.62 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 51 49 52 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 195)
(unspec:V16QI [
(mem (reg:DI 317) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (nil))
(insn 52 51 53 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 197)
(mem:V4SF (and:DI (reg/f:DI 189 [ ivtmp.33 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (expr_list:REG_EQUAL (mem:V4SF (and:DI (symbol_ref:DI
("coeff") [flags 0x80] <var_decl 0xf7d45ee0 coeff>)
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])
(nil)))
(insn 53 52 54 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 198)
(mem:V4SF (and:DI (plus:DI (reg/f:DI 189 [ ivtmp.33 ])
(const_int 12 [0xc]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (expr_list:REG_EQUAL (mem:V4SF (and:DI (const:DI (plus:DI
(symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0 coeff>)
(const_int 12 [0xc])))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])
(nil)))
(insn 54 53 55 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 196)
(unspec:V4SF [
(reg:V4SF 197)
(reg:V4SF 198)
(reg:V16QI 195)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
198)
(expr_list:REG_DEAD (reg:V4SF 197)
(expr_list:REG_DEAD (reg:V16QI 195)
(nil)))))
(insn 55 54 56 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128])
(reg:V4SF 196))
(unspec [
(const_int 0 [0x0])
] 203)
]) 852 {*altivec_stvesfx} (expr_list:REG_DEAD (reg:V4SF 196)
(nil)))
(insn 56 55 57 3 vect-outer-fir2-kernel.c:45 (set (reg:SF 179 [ stmp_var_.89 ])
(mem/c/i:SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])) 328 {*movsf_hardfloat}
(nil))
(insn 57 56 58 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 199)
(neg:DI (reg:DI 192 [ ivtmp.21 ]))) 103 {*negdi2_internal} (nil))
(insn 58 57 59 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 200)
(unspec:V16QI [
(mem (reg:DI 199) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 199)
(nil)))
(insn 59 58 60 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 202)
(mem:V4SF (and:DI (reg:DI 192 [ ivtmp.21 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (expr_list:REG_DEAD (reg:DI 192 [ ivtmp.21 ])
(nil)))
(insn 60 59 61 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 201)
(unspec:V4SF [
(reg:V4SF 202)
(reg:V4SF 190 [ vect_var_.25 ])
(reg:V16QI 200)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
202)
(expr_list:REG_DEAD (reg:V16QI 200)
(nil))))
(insn 61 60 62 3 vect-outer-fir2-kernel.c:45 (set (mem/c/i:SF (plus:DI
(reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])
(reg:SF 179 [ stmp_var_.89 ])) 328 {*movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 179 [ stmp_var_.89 ])
(nil)))
(insn 62 61 63 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (reg:V4SF 203)
(mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128]))
(unspec [
(const_int 0 [0x0])
] 196)
]) 844 {*altivec_lvesfx} (nil))
(insn 63 62 65 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 203)
(vec_duplicate:V4SF (vec_select:SF (reg:V4SF 203)
(parallel [
(const_int 0 [0x0])
])))) 793 {*altivec_vspltsf} (nil))
(insn 65 63 66 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SI 205)
(unspec:V4SI [
(reg:V4SI 319)
(reg:V4SI 319)
] 107)) 772 {altivec_vslw} (expr_list:REG_DEAD (reg:V4SI 319)
(nil)))
(insn 66 65 292 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 204)
(plus:V4SF (mult:V4SF (reg:V4SF 201)
(reg:V4SF 203))
(subreg:V4SF (reg:V4SI 205) 0))) 698 {altivec_vmaddfp}
(expr_list:REG_DEAD (reg:V4SI 205)
(expr_list:REG_DEAD (reg:V4SF 203)
(expr_list:REG_DEAD (reg:V4SF 201)
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 201)
(reg:V4SF 203))
(nil))))))
(insn 292 66 68 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 206)
(reg:V4SF 320)) -1 (nil))
(insn 68 292 69 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 178 [ vect_var_.92
])
(plus:V4SF (reg:V4SF 204)
(reg:V4SF 320))) 660 {addv4sf3} (expr_list:REG_DEAD (reg:V4SF 204)
(expr_list:REG_EQUAL (plus:V4SF (reg:V4SF 204)
(const_vector:V4SF [
(const_double:SF 0.0 [0x0.0p+0])
(const_double:SF 0.0 [0x0.0p+0])
(const_double:SF 0.0 [0x0.0p+0])
(const_double:SF 0.0 [0x0.0p+0])
]))
(nil))))
(insn 69 68 72 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 146 [ ivtmp.200 ])
(plus:DI (reg:DI 187 [ ivtmp.58 ])
(const_int -12 [0xfffffffffffffff4]))) 80 {*adddi3_internal1}
(nil))
(insn 72 69 293 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 176 [ vect_var_.96
])
(mem:V4SF (and:DI (reg:DI 187 [ ivtmp.58 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 293 72 74 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 207)
(reg:DI 321)) -1 (nil))
(insn 74 293 75 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 208)
(unspec:V16QI [
(mem (reg:DI 321) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 207)
(nil)))
(insn 75 74 76 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 210)
(mem:V4SF (and:DI (reg/f:DI 316)
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (expr_list:REG_EQUAL (mem:V4SF (and:DI (const:DI (plus:DI
(symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0 coeff>)
(const_int 4 [0x4])))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])
(nil)))
(insn 76 75 77 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 211)
(mem:V4SF (and:DI (plus:DI (reg/f:DI 316)
(const_int 12 [0xc]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (expr_list:REG_EQUAL (mem:V4SF (and:DI (const:DI (plus:DI
(symbol_ref:DI ("coeff") [flags 0x80] <var_decl 0xf7d45ee0 coeff>)
(const_int 16 [0x10])))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])
(nil)))
(insn 77 76 78 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 209)
(unspec:V4SF [
(reg:V4SF 210)
(reg:V4SF 211)
(reg:V16QI 208)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
211)
(expr_list:REG_DEAD (reg:V4SF 210)
(expr_list:REG_DEAD (reg:V16QI 208)
(nil)))))
(insn 78 77 79 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128])
(reg:V4SF 209))
(unspec [
(const_int 0 [0x0])
] 203)
]) 852 {*altivec_stvesfx} (expr_list:REG_DEAD (reg:V4SF 209)
(nil)))
(insn 79 78 80 3 vect-outer-fir2-kernel.c:45 (set (reg:SF 175 [ stmp_var_.103
])
(mem/c/i:SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])) 328 {*movsf_hardfloat}
(nil))
(insn 80 79 81 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 212)
(neg:DI (reg:DI 146 [ ivtmp.200 ]))) 103 {*negdi2_internal} (nil))
(insn 81 80 82 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 213)
(unspec:V16QI [
(mem (reg:DI 212) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 212)
(nil)))
(insn 82 81 83 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 215)
(mem:V4SF (and:DI (reg:DI 146 [ ivtmp.200 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (expr_list:REG_DEAD (reg:DI 146 [ ivtmp.200 ])
(nil)))
(insn 83 82 84 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 214)
(unspec:V4SF [
(reg:V4SF 215)
(reg:V4SF 176 [ vect_var_.96 ])
(reg:V16QI 213)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
215)
(expr_list:REG_DEAD (reg:V16QI 213)
(nil))))
(insn 84 83 85 3 vect-outer-fir2-kernel.c:45 (set (mem/c/i:SF (plus:DI
(reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])
(reg:SF 175 [ stmp_var_.103 ])) 328 {*movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 175 [ stmp_var_.103 ])
(nil)))
(insn 85 84 86 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (reg:V4SF 216)
(mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128]))
(unspec [
(const_int 0 [0x0])
] 196)
]) 844 {*altivec_lvesfx} (nil))
(insn 86 85 294 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 216)
(vec_duplicate:V4SF (vec_select:SF (reg:V4SF 216)
(parallel [
(const_int 0 [0x0])
])))) 793 {*altivec_vspltsf} (nil))
(insn 294 86 295 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SI 218)
(reg:V4SI 322)) -1 (nil))
(insn 295 294 89 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SI 218)
(reg:V4SI 323)) -1 (nil))
(insn 89 295 90 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 217)
(plus:V4SF (mult:V4SF (reg:V4SF 214)
(reg:V4SF 216))
(subreg:V4SF (reg:V4SI 323) 0))) 698 {altivec_vmaddfp}
(expr_list:REG_DEAD (reg:V4SF 216)
(expr_list:REG_DEAD (reg:V4SF 214)
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 214)
(reg:V4SF 216))
(nil)))))
(insn 90 89 91 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 174 [ vect_var_.106
])
(plus:V4SF (reg:V4SF 178 [ vect_var_.92 ])
(reg:V4SF 217))) 660 {addv4sf3} (expr_list:REG_DEAD (reg:V4SF 217)
(expr_list:REG_DEAD (reg:V4SF 178 [ vect_var_.92 ])
(nil))))
(insn 91 90 296 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 144 [ ivtmp.202 ])
(plus:DI (reg:DI 187 [ ivtmp.58 ])
(const_int -8 [0xfffffffffffffff8]))) 80 {*adddi3_internal1} (nil))
(insn 296 91 94 3 vect-outer-fir2-kernel.c:45 (set (reg/f:DI 173 [ ivtmp.107 ])
(reg:DI 324)) -1 (nil))
(insn 94 296 297 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 172 [
vect_var_.110 ])
(mem:V4SF (and:DI (reg:DI 184 [ ivtmp.65 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 297 94 96 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 219)
(reg:DI 325)) -1 (nil))
(insn 96 297 97 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 220)
(unspec:V16QI [
(mem (reg:DI 325) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 219)
(nil)))
(insn 97 96 98 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 222)
(mem:V4SF (and:DI (reg:DI 324)
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 98 97 99 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 223)
(mem:V4SF (and:DI (plus:DI (reg:DI 324)
(const_int 12 [0xc]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 99 98 100 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 221)
(unspec:V4SF [
(reg:V4SF 222)
(reg:V4SF 223)
(reg:V16QI 220)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
223)
(expr_list:REG_DEAD (reg:V4SF 222)
(expr_list:REG_DEAD (reg:V16QI 220)
(nil)))))
(insn 100 99 101 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128])
(reg:V4SF 221))
(unspec [
(const_int 0 [0x0])
] 203)
]) 852 {*altivec_stvesfx} (expr_list:REG_DEAD (reg:V4SF 221)
(nil)))
(insn 101 100 102 3 vect-outer-fir2-kernel.c:45 (set (reg:SF 171 [
stmp_var_.117 ])
(mem/c/i:SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])) 328 {*movsf_hardfloat}
(nil))
(insn 102 101 103 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 224)
(neg:DI (reg:DI 144 [ ivtmp.202 ]))) 103 {*negdi2_internal} (nil))
(insn 103 102 104 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 225)
(unspec:V16QI [
(mem (reg:DI 224) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 224)
(nil)))
(insn 104 103 105 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 227)
(mem:V4SF (and:DI (reg:DI 144 [ ivtmp.202 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (expr_list:REG_DEAD (reg:DI 144 [ ivtmp.202 ])
(nil)))
(insn 105 104 106 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 226)
(unspec:V4SF [
(reg:V4SF 227)
(reg:V4SF 172 [ vect_var_.110 ])
(reg:V16QI 225)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
227)
(expr_list:REG_DEAD (reg:V16QI 225)
(nil))))
(insn 106 105 107 3 vect-outer-fir2-kernel.c:45 (set (mem/c/i:SF (plus:DI
(reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])
(reg:SF 171 [ stmp_var_.117 ])) 328 {*movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 171 [ stmp_var_.117 ])
(nil)))
(insn 107 106 108 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (reg:V4SF 228)
(mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128]))
(unspec [
(const_int 0 [0x0])
] 196)
]) 844 {*altivec_lvesfx} (nil))
(insn 108 107 111 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 228)
(vec_duplicate:V4SF (vec_select:SF (reg:V4SF 228)
(parallel [
(const_int 0 [0x0])
])))) 793 {*altivec_vspltsf} (nil))
(insn 111 108 112 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 229)
(plus:V4SF (mult:V4SF (reg:V4SF 226)
(reg:V4SF 228))
(subreg:V4SF (reg:V4SI 323) 0))) 698 {altivec_vmaddfp}
(expr_list:REG_DEAD (reg:V4SF 228)
(expr_list:REG_DEAD (reg:V4SF 226)
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 226)
(reg:V4SF 228))
(nil)))))
(insn 112 111 298 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 170 [
vect_var_.120 ])
(plus:V4SF (reg:V4SF 174 [ vect_var_.106 ])
(reg:V4SF 229))) 660 {addv4sf3} (expr_list:REG_DEAD (reg:V4SF 229)
(expr_list:REG_DEAD (reg:V4SF 174 [ vect_var_.106 ])
(nil))))
(insn 298 112 115 3 vect-outer-fir2-kernel.c:45 (set (reg/f:DI 169 [ ivtmp.121
])
(reg:DI 326)) -1 (nil))
(insn 115 298 299 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 168 [
vect_var_.123 ])
(mem:V4SF (and:DI (reg:DI 183 [ ivtmp.66 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 299 115 117 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 231)
(reg:DI 327)) -1 (nil))
(insn 117 299 118 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 232)
(unspec:V16QI [
(mem (reg:DI 327) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 231)
(nil)))
(insn 118 117 119 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 234)
(mem:V4SF (and:DI (reg:DI 326)
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 119 118 120 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 235)
(mem:V4SF (and:DI (plus:DI (reg:DI 326)
(const_int 12 [0xc]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 120 119 121 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 233)
(unspec:V4SF [
(reg:V4SF 234)
(reg:V4SF 235)
(reg:V16QI 232)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
235)
(expr_list:REG_DEAD (reg:V4SF 234)
(expr_list:REG_DEAD (reg:V16QI 232)
(nil)))))
(insn 121 120 122 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128])
(reg:V4SF 233))
(unspec [
(const_int 0 [0x0])
] 203)
]) 852 {*altivec_stvesfx} (expr_list:REG_DEAD (reg:V4SF 233)
(nil)))
(insn 122 121 123 3 vect-outer-fir2-kernel.c:45 (set (reg:SF 167 [
stmp_var_.130 ])
(mem/c/i:SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])) 328 {*movsf_hardfloat}
(nil))
(insn 123 122 124 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 236)
(neg:DI (reg:DI 185 [ ivtmp.62 ]))) 103 {*negdi2_internal} (nil))
(insn 124 123 125 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 237)
(unspec:V16QI [
(mem (reg:DI 236) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 236)
(nil)))
(insn 125 124 126 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 238)
(unspec:V4SF [
(reg:V4SF 190 [ vect_var_.25 ])
(reg:V4SF 168 [ vect_var_.123 ])
(reg:V16QI 237)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V16QI
237)
(expr_list:REG_DEAD (reg:V4SF 190 [ vect_var_.25 ])
(nil))))
(insn 126 125 127 3 vect-outer-fir2-kernel.c:45 (set (mem/c/i:SF (plus:DI
(reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])
(reg:SF 167 [ stmp_var_.130 ])) 328 {*movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 167 [ stmp_var_.130 ])
(nil)))
(insn 127 126 128 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (reg:V4SF 239)
(mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128]))
(unspec [
(const_int 0 [0x0])
] 196)
]) 844 {*altivec_lvesfx} (nil))
(insn 128 127 131 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 239)
(vec_duplicate:V4SF (vec_select:SF (reg:V4SF 239)
(parallel [
(const_int 0 [0x0])
])))) 793 {*altivec_vspltsf} (nil))
(insn 131 128 132 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 240)
(plus:V4SF (mult:V4SF (reg:V4SF 238)
(reg:V4SF 239))
(subreg:V4SF (reg:V4SI 323) 0))) 698 {altivec_vmaddfp}
(expr_list:REG_DEAD (reg:V4SF 239)
(expr_list:REG_DEAD (reg:V4SF 238)
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 238)
(reg:V4SF 239))
(nil)))))
(insn 132 131 300 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 166 [
vect_var_.133 ])
(plus:V4SF (reg:V4SF 170 [ vect_var_.120 ])
(reg:V4SF 240))) 660 {addv4sf3} (expr_list:REG_DEAD (reg:V4SF 240)
(expr_list:REG_DEAD (reg:V4SF 170 [ vect_var_.120 ])
(nil))))
(insn 300 132 135 3 vect-outer-fir2-kernel.c:45 (set (reg/f:DI 165 [ ivtmp.134
])
(reg:DI 328)) -1 (nil))
(insn 135 300 301 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 164 [
vect_var_.136 ])
(mem:V4SF (and:DI (reg:DI 182 [ ivtmp.67 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 301 135 137 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 242)
(reg:DI 329)) -1 (nil))
(insn 137 301 138 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 243)
(unspec:V16QI [
(mem (reg:DI 329) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 242)
(nil)))
(insn 138 137 139 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 245)
(mem:V4SF (and:DI (reg:DI 328)
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 139 138 140 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 246)
(mem:V4SF (and:DI (plus:DI (reg:DI 328)
(const_int 12 [0xc]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 140 139 141 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 244)
(unspec:V4SF [
(reg:V4SF 245)
(reg:V4SF 246)
(reg:V16QI 243)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
246)
(expr_list:REG_DEAD (reg:V4SF 245)
(expr_list:REG_DEAD (reg:V16QI 243)
(nil)))))
(insn 141 140 142 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128])
(reg:V4SF 244))
(unspec [
(const_int 0 [0x0])
] 203)
]) 852 {*altivec_stvesfx} (expr_list:REG_DEAD (reg:V4SF 244)
(nil)))
(insn 142 141 143 3 vect-outer-fir2-kernel.c:45 (set (reg:SF 163 [
stmp_var_.143 ])
(mem/c/i:SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])) 328 {*movsf_hardfloat}
(nil))
(insn 143 142 144 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 247)
(neg:DI (reg:DI 187 [ ivtmp.58 ]))) 103 {*negdi2_internal} (nil))
(insn 144 143 145 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 248)
(unspec:V16QI [
(mem (reg:DI 247) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 247)
(nil)))
(insn 145 144 146 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 249)
(unspec:V4SF [
(reg:V4SF 176 [ vect_var_.96 ])
(reg:V4SF 164 [ vect_var_.136 ])
(reg:V16QI 248)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V16QI
248)
(expr_list:REG_DEAD (reg:V4SF 176 [ vect_var_.96 ])
(nil))))
(insn 146 145 147 3 vect-outer-fir2-kernel.c:45 (set (mem/c/i:SF (plus:DI
(reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])
(reg:SF 163 [ stmp_var_.143 ])) 328 {*movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 163 [ stmp_var_.143 ])
(nil)))
(insn 147 146 148 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (reg:V4SF 250)
(mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128]))
(unspec [
(const_int 0 [0x0])
] 196)
]) 844 {*altivec_lvesfx} (nil))
(insn 148 147 151 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 250)
(vec_duplicate:V4SF (vec_select:SF (reg:V4SF 250)
(parallel [
(const_int 0 [0x0])
])))) 793 {*altivec_vspltsf} (nil))
(insn 151 148 152 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 251)
(plus:V4SF (mult:V4SF (reg:V4SF 249)
(reg:V4SF 250))
(subreg:V4SF (reg:V4SI 323) 0))) 698 {altivec_vmaddfp}
(expr_list:REG_DEAD (reg:V4SF 250)
(expr_list:REG_DEAD (reg:V4SF 249)
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 249)
(reg:V4SF 250))
(nil)))))
(insn 152 151 302 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 162 [
vect_var_.146 ])
(plus:V4SF (reg:V4SF 166 [ vect_var_.133 ])
(reg:V4SF 251))) 660 {addv4sf3} (expr_list:REG_DEAD (reg:V4SF 251)
(expr_list:REG_DEAD (reg:V4SF 166 [ vect_var_.133 ])
(nil))))
(insn 302 152 155 3 vect-outer-fir2-kernel.c:45 (set (reg/f:DI 161 [ ivtmp.147
])
(reg:DI 330)) -1 (nil))
(insn 155 302 303 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 160 [
vect_var_.149 ])
(mem:V4SF (and:DI (reg:DI 181 [ ivtmp.68 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 303 155 157 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 253)
(reg:DI 331)) -1 (nil))
(insn 157 303 158 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 254)
(unspec:V16QI [
(mem (reg:DI 331) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 253)
(nil)))
(insn 158 157 159 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 256)
(mem:V4SF (and:DI (reg:DI 330)
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 159 158 160 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 257)
(mem:V4SF (and:DI (plus:DI (reg:DI 330)
(const_int 12 [0xc]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 160 159 161 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 255)
(unspec:V4SF [
(reg:V4SF 256)
(reg:V4SF 257)
(reg:V16QI 254)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
257)
(expr_list:REG_DEAD (reg:V4SF 256)
(expr_list:REG_DEAD (reg:V16QI 254)
(nil)))))
(insn 161 160 162 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128])
(reg:V4SF 255))
(unspec [
(const_int 0 [0x0])
] 203)
]) 852 {*altivec_stvesfx} (expr_list:REG_DEAD (reg:V4SF 255)
(nil)))
(insn 162 161 163 3 vect-outer-fir2-kernel.c:45 (set (reg:SF 159 [
stmp_var_.156 ])
(mem/c/i:SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])) 328 {*movsf_hardfloat}
(nil))
(insn 163 162 164 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 258)
(neg:DI (reg:DI 184 [ ivtmp.65 ]))) 103 {*negdi2_internal} (nil))
(insn 164 163 165 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 259)
(unspec:V16QI [
(mem (reg:DI 258) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 258)
(nil)))
(insn 165 164 166 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 260)
(unspec:V4SF [
(reg:V4SF 172 [ vect_var_.110 ])
(reg:V4SF 160 [ vect_var_.149 ])
(reg:V16QI 259)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V16QI
259)
(expr_list:REG_DEAD (reg:V4SF 172 [ vect_var_.110 ])
(nil))))
(insn 166 165 167 3 vect-outer-fir2-kernel.c:45 (set (mem/c/i:SF (plus:DI
(reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])
(reg:SF 159 [ stmp_var_.156 ])) 328 {*movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 159 [ stmp_var_.156 ])
(nil)))
(insn 167 166 168 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (reg:V4SF 261)
(mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128]))
(unspec [
(const_int 0 [0x0])
] 196)
]) 844 {*altivec_lvesfx} (nil))
(insn 168 167 171 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 261)
(vec_duplicate:V4SF (vec_select:SF (reg:V4SF 261)
(parallel [
(const_int 0 [0x0])
])))) 793 {*altivec_vspltsf} (nil))
(insn 171 168 172 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 262)
(plus:V4SF (mult:V4SF (reg:V4SF 260)
(reg:V4SF 261))
(subreg:V4SF (reg:V4SI 323) 0))) 698 {altivec_vmaddfp}
(expr_list:REG_DEAD (reg:V4SF 261)
(expr_list:REG_DEAD (reg:V4SF 260)
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 260)
(reg:V4SF 261))
(nil)))))
(insn 172 171 304 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 158 [
vect_var_.159 ])
(plus:V4SF (reg:V4SF 162 [ vect_var_.146 ])
(reg:V4SF 262))) 660 {addv4sf3} (expr_list:REG_DEAD (reg:V4SF 262)
(expr_list:REG_DEAD (reg:V4SF 162 [ vect_var_.146 ])
(nil))))
(insn 304 172 175 3 vect-outer-fir2-kernel.c:45 (set (reg/f:DI 157 [ ivtmp.160
])
(reg:DI 332)) -1 (nil))
(insn 175 304 305 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 156 [
vect_var_.162 ])
(mem:V4SF (and:DI (reg:DI 180 [ ivtmp.69 ])
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 305 175 177 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 264)
(reg:DI 333)) -1 (nil))
(insn 177 305 178 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 265)
(unspec:V16QI [
(mem (reg:DI 333) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 264)
(nil)))
(insn 178 177 179 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 267)
(mem:V4SF (and:DI (reg:DI 332)
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 179 178 180 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 268)
(mem:V4SF (and:DI (plus:DI (reg:DI 332)
(const_int 12 [0xc]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 180 179 181 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 266)
(unspec:V4SF [
(reg:V4SF 267)
(reg:V4SF 268)
(reg:V16QI 265)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
268)
(expr_list:REG_DEAD (reg:V4SF 267)
(expr_list:REG_DEAD (reg:V16QI 265)
(nil)))))
(insn 181 180 182 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128])
(reg:V4SF 266))
(unspec [
(const_int 0 [0x0])
] 203)
]) 852 {*altivec_stvesfx} (expr_list:REG_DEAD (reg:V4SF 266)
(nil)))
(insn 182 181 183 3 vect-outer-fir2-kernel.c:45 (set (reg:SF 155 [
stmp_var_.169 ])
(mem/c/i:SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])) 328 {*movsf_hardfloat}
(nil))
(insn 183 182 184 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 269)
(neg:DI (reg:DI 183 [ ivtmp.66 ]))) 103 {*negdi2_internal} (nil))
(insn 184 183 185 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 270)
(unspec:V16QI [
(mem (reg:DI 269) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 269)
(nil)))
(insn 185 184 186 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 271)
(unspec:V4SF [
(reg:V4SF 168 [ vect_var_.123 ])
(reg:V4SF 156 [ vect_var_.162 ])
(reg:V16QI 270)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V16QI
270)
(expr_list:REG_DEAD (reg:V4SF 168 [ vect_var_.123 ])
(nil))))
(insn 186 185 187 3 vect-outer-fir2-kernel.c:45 (set (mem/c/i:SF (plus:DI
(reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])
(reg:SF 155 [ stmp_var_.169 ])) 328 {*movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 155 [ stmp_var_.169 ])
(nil)))
(insn 187 186 188 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (reg:V4SF 272)
(mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128]))
(unspec [
(const_int 0 [0x0])
] 196)
]) 844 {*altivec_lvesfx} (nil))
(insn 188 187 191 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 272)
(vec_duplicate:V4SF (vec_select:SF (reg:V4SF 272)
(parallel [
(const_int 0 [0x0])
])))) 793 {*altivec_vspltsf} (nil))
(insn 191 188 192 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 273)
(plus:V4SF (mult:V4SF (reg:V4SF 271)
(reg:V4SF 272))
(subreg:V4SF (reg:V4SI 323) 0))) 698 {altivec_vmaddfp}
(expr_list:REG_DEAD (reg:V4SF 272)
(expr_list:REG_DEAD (reg:V4SF 271)
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 271)
(reg:V4SF 272))
(nil)))))
(insn 192 191 306 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 154 [
vect_var_.172 ])
(plus:V4SF (reg:V4SF 158 [ vect_var_.159 ])
(reg:V4SF 273))) 660 {addv4sf3} (expr_list:REG_DEAD (reg:V4SF 273)
(expr_list:REG_DEAD (reg:V4SF 158 [ vect_var_.159 ])
(nil))))
(insn 306 192 307 3 vect-outer-fir2-kernel.c:45 (set (reg/f:DI 153 [ ivtmp.173
])
(reg:DI 334)) -1 (nil))
(insn 307 306 195 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 275)
(reg:DI 335)) -1 (nil))
(insn 195 307 196 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 276)
(unspec:V16QI [
(mem (reg:DI 335) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 275)
(nil)))
(insn 196 195 197 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 278)
(mem:V4SF (and:DI (reg:DI 334)
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 197 196 198 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 279)
(mem:V4SF (and:DI (plus:DI (reg:DI 334)
(const_int 12 [0xc]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 198 197 199 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 277)
(unspec:V4SF [
(reg:V4SF 278)
(reg:V4SF 279)
(reg:V16QI 276)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
279)
(expr_list:REG_DEAD (reg:V4SF 278)
(expr_list:REG_DEAD (reg:V16QI 276)
(nil)))))
(insn 199 198 200 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128])
(reg:V4SF 277))
(unspec [
(const_int 0 [0x0])
] 203)
]) 852 {*altivec_stvesfx} (expr_list:REG_DEAD (reg:V4SF 277)
(nil)))
(insn 200 199 201 3 vect-outer-fir2-kernel.c:45 (set (reg:SF 152 [
stmp_var_.182 ])
(mem/c/i:SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])) 328 {*movsf_hardfloat}
(nil))
(insn 201 200 202 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 280)
(neg:DI (reg:DI 182 [ ivtmp.67 ]))) 103 {*negdi2_internal} (nil))
(insn 202 201 203 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 281)
(unspec:V16QI [
(mem (reg:DI 280) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 280)
(nil)))
(insn 203 202 204 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 283)
(mem:V4SF (and:DI (plus:DI (reg:DI 187 [ ivtmp.58 ])
(const_int 24 [0x18]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 204 203 205 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 282)
(unspec:V4SF [
(reg:V4SF 164 [ vect_var_.136 ])
(reg:V4SF 283)
(reg:V16QI 281)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
283)
(expr_list:REG_DEAD (reg:V16QI 281)
(expr_list:REG_DEAD (reg:V4SF 164 [ vect_var_.136 ])
(nil)))))
(insn 205 204 206 3 vect-outer-fir2-kernel.c:45 (set (mem/c/i:SF (plus:DI
(reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])
(reg:SF 152 [ stmp_var_.182 ])) 328 {*movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 152 [ stmp_var_.182 ])
(nil)))
(insn 206 205 207 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (reg:V4SF 284)
(mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128]))
(unspec [
(const_int 0 [0x0])
] 196)
]) 844 {*altivec_lvesfx} (nil))
(insn 207 206 210 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 284)
(vec_duplicate:V4SF (vec_select:SF (reg:V4SF 284)
(parallel [
(const_int 0 [0x0])
])))) 793 {*altivec_vspltsf} (nil))
(insn 210 207 211 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 285)
(plus:V4SF (mult:V4SF (reg:V4SF 282)
(reg:V4SF 284))
(subreg:V4SF (reg:V4SI 323) 0))) 698 {altivec_vmaddfp}
(expr_list:REG_DEAD (reg:V4SF 284)
(expr_list:REG_DEAD (reg:V4SF 282)
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 282)
(reg:V4SF 284))
(nil)))))
(insn 211 210 308 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 151 [
vect_var_.185 ])
(plus:V4SF (reg:V4SF 154 [ vect_var_.172 ])
(reg:V4SF 285))) 660 {addv4sf3} (expr_list:REG_DEAD (reg:V4SF 285)
(expr_list:REG_DEAD (reg:V4SF 154 [ vect_var_.172 ])
(nil))))
(insn 308 211 309 3 vect-outer-fir2-kernel.c:45 (set (reg/f:DI 150 [ ivtmp.186
])
(reg:DI 336)) -1 (nil))
(insn 309 308 214 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 287)
(reg:DI 337)) -1 (nil))
(insn 214 309 215 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 288)
(unspec:V16QI [
(mem (reg:DI 337) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 287)
(nil)))
(insn 215 214 216 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 290)
(mem:V4SF (and:DI (reg:DI 336)
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 216 215 217 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 291)
(mem:V4SF (and:DI (plus:DI (reg:DI 336)
(const_int 12 [0xc]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 217 216 218 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 289)
(unspec:V4SF [
(reg:V4SF 290)
(reg:V4SF 291)
(reg:V16QI 288)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
291)
(expr_list:REG_DEAD (reg:V4SF 290)
(expr_list:REG_DEAD (reg:V16QI 288)
(nil)))))
(insn 218 217 219 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128])
(reg:V4SF 289))
(unspec [
(const_int 0 [0x0])
] 203)
]) 852 {*altivec_stvesfx} (expr_list:REG_DEAD (reg:V4SF 289)
(nil)))
(insn 219 218 220 3 vect-outer-fir2-kernel.c:45 (set (reg:SF 149 [
stmp_var_.195 ])
(mem/c/i:SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])) 328 {*movsf_hardfloat}
(nil))
(insn 220 219 221 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 292)
(neg:DI (reg:DI 181 [ ivtmp.68 ]))) 103 {*negdi2_internal} (nil))
(insn 221 220 222 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 293)
(unspec:V16QI [
(mem (reg:DI 292) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 292)
(nil)))
(insn 222 221 223 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 295)
(mem:V4SF (and:DI (plus:DI (reg:DI 187 [ ivtmp.58 ])
(const_int 28 [0x1c]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 223 222 224 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 294)
(unspec:V4SF [
(reg:V4SF 160 [ vect_var_.149 ])
(reg:V4SF 295)
(reg:V16QI 293)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
295)
(expr_list:REG_DEAD (reg:V16QI 293)
(expr_list:REG_DEAD (reg:V4SF 160 [ vect_var_.149 ])
(nil)))))
(insn 224 223 225 3 vect-outer-fir2-kernel.c:45 (set (mem/c/i:SF (plus:DI
(reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])
(reg:SF 149 [ stmp_var_.195 ])) 328 {*movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 149 [ stmp_var_.195 ])
(nil)))
(insn 225 224 226 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (reg:V4SF 296)
(mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128]))
(unspec [
(const_int 0 [0x0])
] 196)
]) 844 {*altivec_lvesfx} (nil))
(insn 226 225 229 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 296)
(vec_duplicate:V4SF (vec_select:SF (reg:V4SF 296)
(parallel [
(const_int 0 [0x0])
])))) 793 {*altivec_vspltsf} (nil))
(insn 229 226 230 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 297)
(plus:V4SF (mult:V4SF (reg:V4SF 294)
(reg:V4SF 296))
(subreg:V4SF (reg:V4SI 323) 0))) 698 {altivec_vmaddfp}
(expr_list:REG_DEAD (reg:V4SF 296)
(expr_list:REG_DEAD (reg:V4SF 294)
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 294)
(reg:V4SF 296))
(nil)))))
(insn 230 229 310 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 148 [
vect_var_.198 ])
(plus:V4SF (reg:V4SF 151 [ vect_var_.185 ])
(reg:V4SF 297))) 660 {addv4sf3} (expr_list:REG_DEAD (reg:V4SF 297)
(expr_list:REG_DEAD (reg:V4SF 151 [ vect_var_.185 ])
(nil))))
(insn 310 230 311 3 vect-outer-fir2-kernel.c:45 (set (reg/f:DI 147 [ ivtmp.199
])
(reg:DI 338)) -1 (nil))
(insn 311 310 233 3 vect-outer-fir2-kernel.c:45 (set (reg:DI 299)
(reg:DI 339)) -1 (nil))
(insn 233 311 234 3 vect-outer-fir2-kernel.c:45 (set (reg:V16QI 300)
(unspec:V16QI [
(mem (reg:DI 339) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 299)
(nil)))
(insn 234 233 235 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 302)
(mem:V4SF (and:DI (reg:DI 338)
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 235 234 236 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 303)
(mem:V4SF (and:DI (plus:DI (reg:DI 338)
(const_int 12 [0xc]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (expr_list:REG_DEAD (reg/f:DI 147 [ ivtmp.199 ])
(nil)))
(insn 236 235 237 3 vect-outer-fir2-kernel.c:45 (set (reg:V4SF 301)
(unspec:V4SF [
(reg:V4SF 302)
(reg:V4SF 303)
(reg:V16QI 300)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
303)
(expr_list:REG_DEAD (reg:V4SF 302)
(expr_list:REG_DEAD (reg:V16QI 300)
(nil)))))
(insn 237 236 238 3 vect-outer-fir2-kernel.c:45 (parallel [
(set (mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128])
(reg:V4SF 301))
(unspec [
(const_int 0 [0x0])
] 203)
]) 852 {*altivec_stvesfx} (expr_list:REG_DEAD (reg:V4SF 301)
(nil)))
(insn 238 237 239 3 vect-outer-fir2-kernel.c:45 (set (reg:SF 188 [ stmp_var_.39
])
(mem/c/i:SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])) 328 {*movsf_hardfloat}
(nil))
(insn 239 238 240 3 vect-outer-fir2-kernel.c:47 (set (reg:DI 304)
(neg:DI (reg:DI 180 [ ivtmp.69 ]))) 103 {*negdi2_internal} (nil))
(insn 240 239 241 3 vect-outer-fir2-kernel.c:47 (set (reg:V16QI 305)
(unspec:V16QI [
(mem (reg:DI 304) [0 S0 A8])
] 195)) 840 {altivec_lvsr} (expr_list:REG_DEAD (reg:DI 304)
(nil)))
(insn 241 240 242 3 vect-outer-fir2-kernel.c:47 (set (reg:V4SF 307)
(mem:V4SF (and:DI (plus:DI (reg:DI 187 [ ivtmp.58 ])
(const_int 32 [0x20]))
(const_int -16 [0xfffffffffffffff0])) [3 S16 A128])) 646
{altivec_lvx_v4sf} (nil))
(insn 242 241 243 3 vect-outer-fir2-kernel.c:47 (set (reg:V4SF 306)
(unspec:V4SF [
(reg:V4SF 156 [ vect_var_.162 ])
(reg:V4SF 307)
(reg:V16QI 305)
] 215)) 857 {vec_realign_load_v4sf} (expr_list:REG_DEAD (reg:V4SF
307)
(expr_list:REG_DEAD (reg:V16QI 305)
(expr_list:REG_DEAD (reg:V4SF 156 [ vect_var_.162 ])
(nil)))))
(insn 243 242 244 3 vect-outer-fir2-kernel.c:47 (set (mem/c/i:SF (plus:DI
(reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S4 A128])
(reg:SF 188 [ stmp_var_.39 ])) 328 {*movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 188 [ stmp_var_.39 ])
(nil)))
(insn 244 243 245 3 vect-outer-fir2-kernel.c:47 (parallel [
(set (reg:V4SF 308)
(mem/c/i:V4SF (plus:DI (reg/f:DI 113 sfp)
(const_int 48 [0x30])) [3 S16 A128]))
(unspec [
(const_int 0 [0x0])
] 196)
]) 844 {*altivec_lvesfx} (nil))
(insn 245 244 312 3 vect-outer-fir2-kernel.c:47 (set (reg:V4SF 308)
(vec_duplicate:V4SF (vec_select:SF (reg:V4SF 308)
(parallel [
(const_int 0 [0x0])
])))) 793 {*altivec_vspltsf} (nil))
(insn 312 245 248 3 vect-outer-fir2-kernel.c:47 (set (reg:V4SI 319)
(reg:V4SI 322)) -1 (nil))
(insn 248 312 249 3 vect-outer-fir2-kernel.c:47 (set (reg:V4SF 309)
(plus:V4SF (mult:V4SF (reg:V4SF 306)
(reg:V4SF 308))
(subreg:V4SF (reg:V4SI 323) 0))) 698 {altivec_vmaddfp}
(expr_list:REG_DEAD (reg:V4SF 308)
(expr_list:REG_DEAD (reg:V4SF 306)
(expr_list:REG_DEAD (reg:V4SI 218)
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 306)
(reg:V4SF 308))
(nil))))))
(insn 249 248 251 3 vect-outer-fir2-kernel.c:47 (set (reg:V4SF 311)
(plus:V4SF (reg:V4SF 309)
(reg:V4SF 148 [ vect_var_.198 ]))) 660 {addv4sf3}
(expr_list:REG_DEAD (reg:V4SF 309)
(expr_list:REG_DEAD (reg:V4SF 148 [ vect_var_.198 ])
(nil))))
(insn 251 249 252 3 vect-outer-fir2-kernel.c:47 (set (reg:V4SF 313)
(plus:V4SF (reg:V4SF 311)
(reg:V4SF 320))) 660 {addv4sf3} (expr_list:REG_DEAD (reg:V4SF 311)
(expr_list:REG_DEAD (reg:V4SF 206)
(expr_list:REG_EQUAL (plus:V4SF (reg:V4SF 311)
(const_vector:V4SF [
(const_double:SF 0.0 [0x0.0p+0])
(const_double:SF 0.0 [0x0.0p+0])
(const_double:SF 0.0 [0x0.0p+0])
(const_double:SF 0.0 [0x0.0p+0])
]))
(nil)))))
(insn 252 251 253 3 vect-outer-fir2-kernel.c:47 (set (mem:V4SF (reg:DI 186 [
ivtmp.59 ]) [3 S16 A128])
(reg:V4SF 313)) 650 {altivec_stvx_v4sf} (expr_list:REG_DEAD (reg:V4SF
313)
(nil)))
(insn 253 252 254 3 vect-outer-fir2-kernel.c:47 (set (reg:DI 187 [ ivtmp.58 ])
(plus:DI (reg:DI 187 [ ivtmp.58 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
(insn 254 253 255 3 vect-outer-fir2-kernel.c:47 (set (reg:DI 186 [ ivtmp.59 ])
(plus:DI (reg:DI 186 [ ivtmp.59 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
(insn 255 254 256 3 vect-outer-fir2-kernel.c:47 (set (reg:DI 185 [ ivtmp.62 ])
(plus:DI (reg:DI 185 [ ivtmp.62 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
(insn 256 255 257 3 vect-outer-fir2-kernel.c:47 (set (reg:DI 184 [ ivtmp.65 ])
(plus:DI (reg:DI 184 [ ivtmp.65 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
(insn 257 256 258 3 vect-outer-fir2-kernel.c:47 (set (reg:DI 183 [ ivtmp.66 ])
(plus:DI (reg:DI 183 [ ivtmp.66 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
(insn 258 257 259 3 vect-outer-fir2-kernel.c:47 (set (reg:DI 182 [ ivtmp.67 ])
(plus:DI (reg:DI 182 [ ivtmp.67 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
(insn 259 258 260 3 vect-outer-fir2-kernel.c:47 (set (reg:DI 181 [ ivtmp.68 ])
(plus:DI (reg:DI 181 [ ivtmp.68 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
(insn 260 259 262 3 vect-outer-fir2-kernel.c:47 (set (reg:DI 180 [ ivtmp.69 ])
(plus:DI (reg:DI 180 [ ivtmp.69 ])
(const_int 16 [0x10]))) 80 {*adddi3_internal1} (nil))
(insn 262 260 264 3 vect-outer-fir2-kernel.c:47 (use (const:DI (plus:DI
(symbol_ref:DI ("fir_out") [flags 0x80] <var_decl 0xf7d571c0 fir_out>)
(const_int 160 [0xa0])))) -1 (nil))
(insn 264 262 265 3 vect-outer-fir2-kernel.c:47 (set (reg:CC 315)
(compare:CC (reg:DI 186 [ ivtmp.59 ])
(reg/f:DI 318))) 459 {*cmpdi_internal1} (expr_list:REG_EQUAL
(compare:CC (reg:DI 186 [ ivtmp.59 ])
(const:DI (plus:DI (symbol_ref:DI ("fir_out") [flags 0x80]
<var_decl 0xf7d571c0 fir_out>)
(const_int 160 [0xa0]))))
(nil)))
(jump_insn 265 264 291 3 vect-outer-fir2-kernel.c:47 (set (pc)
(if_then_else (ne (reg:CC 315)
(const_int 0 [0x0]))
(label_ref:DI 291)
(pc))) 546 {*rs6000.md:13881} (expr_list:REG_DEAD (reg:CC 315)
(expr_list:REG_BR_PROB (const_int 9750 [0x2616])
(nil))))
;; End of basic block 3 -> ( 5 4)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
334 335 336 337 338 339
;; live out 180 181 182 183 184 185 186 187 319
;; Succ edge 5 [97.5%] (dfs_back)
;; Succ edge 4 [2.5%] (fallthru,loop_exit)
;; Start of basic block ( 3) -> 5
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u-1(1){ }u-1(31){ }u-1(67){ }u-1(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
334 335 336 337 338 339
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def
;; live in 180 181 182 183 184 185 186 187 319
;; live gen
;; live kill
;; Pred edge 3 [97.5%] (dfs_back)
(code_label 291 265 290 5 4 "" [1 uses])
(note 290 291 273 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
;; End of basic block 5 -> ( 3)
;; lr out 1 [1] 31 [31] 67 [ap] 113 [sfp] 180 181 182 183 184 185 186
187 189 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
334 335 336 337 338 339
;; live out 180 181 182 183 184 185 186 187 319
;; Succ edge 3 [100.0%] (fallthru)
;; Start of basic block ( 3) -> 4
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u347(1){ }u348(31){ }u349(67){ }u350(113){ }}
;; lr in 1 [1] 31 [31] 67 [ap] 109 [vrsave] 110 [vscr] 113 [sfp]
;; lr use 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; lr def
;; live in 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; live gen
;; live kill
;; Pred edge 3 [2.5%] (fallthru,loop_exit)
(note 273 290 0 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
;; End of basic block 4 -> ( 1)
;; lr out 1 [1] 31 [31] 67 [ap] 109 [vrsave] 110 [vscr] 113 [sfp]
;; live out 1 [1] 31 [31] 67 [ap] 113 [sfp]
;; Succ edge EXIT [100.0%] (fallthru)
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=33224