[Bug c/29932] New: avr-gcc wrongly optimizes bit sets/resets for IO register 0x20

["mlitwack at employees dot org" <gcc-bugzilla at gcc dot gnu dot org>]

avr-gcc tries to optimize bit sets and resets to IO register 0x20 (PCMSK1 in
the ATtiny24) into sbi/cbi instructions.  However, sbi/cbi are not suitable for
registers >= 0x20.

IO registers 0x1f and 0x21 are handled correctly, so it appears to be just
register address 0x20.

Here is an example that will fail (filtered out from avr-libc):

------------------
typedef unsigned char uint8_t;
#define _MMIO_BYTE(mem_addr) (*(volatile uint8_t *)(mem_addr))
#define _SFR_IO8(io_addr) _MMIO_BYTE((io_addr) + 0x20)

#define PCMSK1  _SFR_IO8(0x20)

main()
{
  PCMSK1 |= 0x01;
}
------------------

$ avr-gcc -Os fail.c
/tmp/ccJwjyqk.s: Assembler messages:
/tmp/ccJwjyqk.s:19: Error: number must be less than 32

No optimization will work fine as will other values for PCMSK1.

Using gcc snapshot from 20061014.

-mark


-- 
           Summary: avr-gcc wrongly optimizes bit sets/resets for IO
                    register 0x20
           Product: gcc
           Version: 4.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: mlitwack at employees dot org
 GCC build triplet: i586-linux-gnu
  GCC host triplet: i586-linux-gnu
GCC target triplet: avr-unknown-none


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29932