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[Bug middle-end/28690] New: Performace problem with indexed load/stores on powerpc


On some powerpc processors, it is very desirable for performance reasons, to
have the base pointer for an indexed load/store insn to be in the rA position
rather than the rB position (example insn shown below).

    lwzx rD,rA,rB

For some test cases, we get this right, but for the following test case, we get
it wrong (regardless of -m32 or -m64):

int indexedload (int *x, int i)
{
  return x[i];
}

Results in the following powerpc asm:

indexedload:
        slwi r4,r4,2
        lwzx r3,r4,r3   # We want r3,r3,r4
        blr

Dan Berlin tracked one problem down to the reassociation pass ignoring non
integral types like pointers.  His patch (I'll let Dan attach it here) fixed
the ordering of the address calc at the end of tree-ssa, but the rtl expanders
seem to be undoing this change so we still end up with the wrong ordering on
the lwzx insn.


-- 
           Summary: Performace problem with indexed load/stores on powerpc
           Product: gcc
           Version: 4.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: bergner at vnet dot ibm dot com
 GCC build triplet: powerpc64-linux
  GCC host triplet: powerpc64-linux
GCC target triplet: powerpc64-linux


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=28690


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