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[Bug target/25212] [4.1/4.2 Regression] unrecognizable insn for facerec with odd optimization set



------- Comment #5 from amodra at bigpond dot net dot au  2005-12-02 01:22 -------
The instruction in question looks like this after local reg alloc, both base
and index don't get a hard register.

(insn:HI 289 292 497 28 (set (reg:V4SF 137 [ vect_var_.102 ])
        (mem:V4SF (and:SI (plus:SI (reg/v/f:SI 193 [ a5 ])
                    (reg:SI 141 [ base_off.93 ]))
                (const_int -16 [0xfffffffffffffff0])) [4 S16 A128])) 628
{altivec_lvx_v4sf} (insn_list:REG_DEP_TRUE 287 (nil))
    (nil))

Global alloc decides to put reg 193 into lr..

Which reload notices as invalid:

Reloads for insn # 289
Reload 0: reload_in (SI) = (reg/v/f:SI 65 lr [orig:193 a5 ] [193])
        GENERAL_REGS, RELOAD_FOR_INPUT_ADDRESS (opnum = 1)
        reload_in_reg: (reg/v/f:SI 65 lr [orig:193 a5 ] [193])
        reload_reg_rtx: (reg:SI 26 26)

But of course the instruction doesn't have lr replaced by the time we try to
match constraints, leading to reload trying to put the whole address expression
into another reload reg.

Reload 1: reload_in (SI) = (and:SI (plus:SI (reg/v/f:SI 65 lr [orig:193 a5 ]
[193])
[snip]

The pr24997 trick of recognising non-canonical rtl generated by reload won't
work here, unfortunately.  Maybe we can look through the reloads already pushed
to decide if the address will be OK after substitution..


-- 

amodra at bigpond dot net dot au changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         AssignedTo|unassigned at gcc dot gnu   |amodra at bigpond dot net
                   |dot org                     |dot au
             Status|UNCONFIRMED                 |ASSIGNED
     Ever Confirmed|0                           |1
   Last reconfirmed|0000-00-00 00:00:00         |2005-12-02 01:22:52
               date|                            |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=25212


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