[Bug rtl-optimization/6585] Redundant store/load instruction pairs on ix86

["pinskia at gcc dot gnu dot org" <gcc-bugzilla at gcc dot gnu dot org>]

------- Additional Comments From pinskia at gcc dot gnu dot org  2004-10-11 02:57 -------
Here is the latest asm from the mainline:
mul:
        subl    $20, %esp
        movl    32(%esp), %ecx
        movl    24(%esp), %eax
        movl    %ebx, 8(%esp)
        movl    36(%esp), %ebx
        movl    %edi, 12(%esp)
        movl    24(%esp), %edi
        movl    %ebp, 16(%esp)
        mull    %ecx
        imull   28(%esp), %ecx
        imull   %ebx, %edi
        movl    8(%esp), %ebx
        movl    %edx, %ebp
        movl    %eax, (%esp)
        addl    %edi, %ebp
        movl    (%esp), %eax
        leal    (%ebp,%ecx), %ecx
        movl    12(%esp), %edi
        movl    %ecx, 4(%esp)
        movl    16(%esp), %ebp
        movl    4(%esp), %edx
        addl    $20, %esp
        ret

-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=6585