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[Bug target/14702] New: wrong definitions of instructions mmx_pshufw, sse2_pshufd, sse2_pshuflw, sse2_pshufhw
- From: "1319 at bot dot ru" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 24 Mar 2004 02:21:32 -0000
- Subject: [Bug target/14702] New: wrong definitions of instructions mmx_pshufw, sse2_pshufd, sse2_pshuflw, sse2_pshufhw
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
According to various documents from intel and AMD source argument of pshufd,
pshuflw, pshufhw, pshufw instructions can be register or memory argument (and
not necessarily same register). So i386.md should be fixed:
--- i386.md.~1.520.~ 2004-03-19 02:56:10.000000000 +0300
+++ i386.md 2004-03-24 05:01:41.027804888 +0300
@@ -20576,7 +20576,7 @@
(define_insn "mmx_pshufw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
- (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
+ (unspec:V4HI [(match_operand:V4HI 1 "nonimmediate_operand" "ym")
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_SHUFFLE))]
"TARGET_SSE || TARGET_3DNOW_A"
@@ -22273,7 +22273,7 @@
(define_insn "sse2_pshufd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
+ (unspec:V4SI [(match_operand:V4SI 1 "nonimmediate_operand" "xm")
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_SHUFFLE))]
"TARGET_SSE2"
@@ -22283,7 +22283,7 @@
(define_insn "sse2_pshuflw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
- (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
+ (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_PSHUFLW))]
"TARGET_SSE2"
@@ -22293,7 +22293,7 @@
(define_insn "sse2_pshufhw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
- (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
+ (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_PSHUFHW))]
"TARGET_SSE2"
I will send this patch to gcc-patches soon. I tested this with my mmx cpu burner
and it gives identical results and zero speed difference (probably because it is
difficult task -- to fill athlon 3-way decoder).
--
Summary: wrong definitions of instructions mmx_pshufw,
sse2_pshufd, sse2_pshuflw, sse2_pshufhw
Product: gcc
Version: 3.3.4
Status: UNCONFIRMED
Severity: normal
Priority: P2
Component: target
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: 1319 at bot dot ru
CC: gcc-bugs at gcc dot gnu dot org
GCC host triplet: i686-pc-linux-gnu
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14702