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[Bug c/12080] arm-elf-gcc-3.2 generates wrong interrupt code w/o optimizations on
- From: "pinskia at gcc dot gnu dot org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 27 Aug 2003 15:36:25 -0000
- Subject: [Bug c/12080] arm-elf-gcc-3.2 generates wrong interrupt code w/o optimizations on
- References: <20030827152130.12080.jamesl@appliedminds.com>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12080
pinskia at gcc dot gnu dot org changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |WAITING
------- Additional Comments From pinskia at gcc dot gnu dot org 2003-08-27 15:36 -------
On the mainline (20030806) I get this:
str ip, [sp, #-4]!
mov ip, sp
stmfd sp!, {r3, fp, ip, lr, pc}
sub fp, ip, #4
sub sp, sp, #4
mvn r3, #65280
sub r3, r3, #199
ldr r3, [r3, #0]
str r3, [fp, #-20]
ldmea fp, {r3, fp, sp, lr}
ldmfd sp!, {ip}
subs pc, lr, #4
But I think the load from fp is okay since fp is set above to fp-4, above that fp = ip, before the
store to sp (which increments sp), ip = sp. The load is still there in the mainline.
What do you think?