Re: SH target - disable @(r0,rm) addressing mode?

[<tm_gccmail at mail dot kloo dot net>]

On Wed, 5 Feb 2003, Joern Rennecke wrote:

> tm_gccmail@mail.kloo.net wrote:
> > 
...
> > The basic problem seems to be an overdependency on the dual-register
> > addressing
> > mode @(r0,rm). The problem is the first register must be r0, so this leads
> > to an overusage of r0, which leaves no placement freedom for the
> > instruction
> > scheduler. The processor appears to be only single-issuing in large blocks
> > of code due to this problem.
> 
> I don't think the problem is really so much that this addressing mode is used,
> as that the addresses are calculated and kept in r0 all the time.
> Since a general purposes register-register move is mt and has latency 0, i.e.
> it can be paired with anything and the result is immediately available, a
> judicously placed move from another register into r0 could solve the problem.
> So before / during reload, we could say that the SH4 has a 3-address add and
> split that post-reload to
> mov rn,rd
> add rm,rd
> Or we could allow an indexed load using registers other than r0, and show
> that r0 is clobbered if a register other than r0 is loaded.

The generalized @(rm,rn) approach seems better than faking a 3AC add
because there's only one extra instruction generated versus two.
What are the possible side effects of doing this?

Toshi