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Re: middle-end/6180: Infinite loop in cc1 during dbr pass
- From: "David S. Miller" <davem at redhat dot com>
- To: law at redhat dot com
- Cc: dave at hiauly1 dot hia dot nrc dot ca, gcc-bugs at gcc dot gnu dot org, gcc at gcc dot gnu dot org, rth at redhat dot com
- Date: Tue, 04 Jun 2002 13:50:10 -0700 (PDT)
- Subject: Re: middle-end/6180: Infinite loop in cc1 during dbr pass
- References: <20020604.125117.48806435.davem@redhat.com><6946.1023223613@porcupine.cygnus.com>
From: law@redhat.com
Date: Tue, 04 Jun 2002 14:46:53 -0600
> This could also, for example, make it much more easier to teach the
> generic instruction scheduler how to do delay slotting so we can
> obliterate reorg.
Oh man. Zapping reorg is conceptually simple if you look at it from
the right angle (ie dependency graphs). It'd also be a hell of a lot
faster.
Pre-delay slots fall right out of that too :-)